MA8251
5. AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Condition
t0
t0
tR, tF
tDTX
tTPW
Clock high pulse width
Clock low pulse width
Clock rise and fall time
100
100
-
-
-
-
20
1
nS
nS
nS
µS
-
-
-
-
TxD delay from falling edge of TxC
Transmitter input clock pulse width
12xosc
1xosc
-
-
-
-
1 x baud rate
16 x and 64 x baud rate
tTPD
tRPW
tRPD
Transmitter input clock pulse delay
Receive input clock pulse width
Receive input clock pulse delay
15xosc
3xosc
12xosc
1xosc
15xosc
3xosc
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
-
ns
1 x baud rate
16 x and 64 x baud rate
1 x baud rate
16 x and 64 x baud rate
1 x baud rate
16 x and 64 x baud rate
Note 6
tTxRDY
tTxRDY CLEAR
tRxRDY
tRxRDY CLEAR
tTxEMPTY
tWC
TxRDY pin delay from CENTER of last bit
TxRDY fall from falling WRN
RxRDY pin delay from center of last bit
RxRDY fall from falling RDN
-
-
-
-
8xosc
50
26xosc
50
Note 6
Note 6
Note 6
TxEMPTY from centre of last bit
Control delay from rising edge of WRN
Control to RDN set-up time (DSR, CTS)
Address stable before RDN (CSN, CDN)
Address hold time from RDN (CSN, CDN)
Address stable before WRN
20xosc
8xosc
20xosc
-
-
-
-
-
-
-
-
Note 6
Note 6
Note 6
Note 1
tCR
tAR
tRA
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
Note 1
tAW
tWA
tRR
tRD
0
0
-
-
-
30
45
-
-
-
-
-
-
Address hold time from WRN
RDN/WRN pulse width
Data delay fromRDN falling
20
-
10
15
5
Note 2
Note 7
-
tDF
RDN rising to data floating
tDW
tWD
tRV
Data set-up time to WRN rising
Data hold time from WRN rising
Recovery time between writes (not shown)
-
6xosc
Note 3
Notes: 1. CSN and Command/Data are considered as addresses.
2. Assumes that address is valid before RDN goes low.
3. This recovery time is for Mode Initialisation only. Write data is allowed when TxRDY = 1. Recovery time between
writes for Asynchronous Mode is 8xosc and for Synchronous Mode is 16xosc.
4. The TxC and RxC frequencies have the following limitation with respect to clock: For 1 x baudrate, fTX or fRX£1/(30osc):
For 16 x and 64 x baud rate, fTX or fRX £1/(4.5osc).
5. Reset Pulse Width = 6osc minimum; System clock must be running during Reset.
6. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
7. Data Bus connected to VDD via loads of 680W(minimum).
Mil-Std-883, method 5005, subgroups 9, 10, 11
Figure 22: AC Electrical Characteristics
Parameter
Min.
Max.
Units
Conditions
Clock Frequency (osc)
-
5
MHz
-
Transmitter input clock frequency
DC
DC
DC
64
310
615
kHz
kHz
kHz
1 x baud rate
16 x baud rate
64 x baud rate
Receiver input clock frequency
DC
DC
DC
64
310
615
kHz
kHz
kHz
1x baud rate
16 x baud rate
64 x baud rate
Mil-Std-883, method 5005, subgroups 7, 8A, 8B
Figure 23: Operating AC Electrical Characteristics
15
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