MA8251
3.12 STATUS READ DEFINITION
In data communication systems it is often necessary to
examine the status of the active device to ascertain if errors
have occurred or other conditions that require the processor’s
attention. The MA8251 has facilities that allow the programmer
to read the status of the device at any time during the
functional operation. (Status update is inhibited during status
read).
A normal read command is issued by the CPU with CDN
high to accomplish this function.
Some of the bits in the Status Read Format have identical
meanings to external output pins so that the MA8251 can be
used in a completely polled or interrupt-driven environment.
TxRDY is an exception.
Note that status update can have a maximum delay of 28
clock periods from the actual event affecting the status.
3.13 STATUS READ FORMAT
D7
D6
D5
D4
D3
D2
D1
D0
DSR SYNDET
BRKDET
FE
OE
PE
Tx
EMPTY
RxRDY TxRDY
Note 1
Same as I/O pins
PARITY ERROR
The PE flag is set when the
parity error is detected. It is
reset by the ER bit of the
Command Instruction. PE does
not inhibit the operation of the
MA8251.
OVERRUN ERROR
The OE flag is set when the
CPU does not read a character
before the next one becomes
available. It is reset by the ER
bit of the Command Instruction
OE does not inhibit operation
of the MA8251, however the
previously overrun character is
lost.
FRAMING ERROR (ASYNC
ONLY)
The FE flag is set when a valid
Stop bit is not detected at the
end of every character. It is
reset by the ER bit of the
Command Instruction. FE does
not inhibit the operation of the
MA8251.
DATA SET READY
Indicates that the DSR is at a
zero level.
Note 1: TxRDY status bit has different meanings from the TxRDY output pin. The former
is not conditioned by CTS and TxEN, the latter is conditioned by both CTS and TxEN.
ie. TxRDY status bit 0 DB buffer empty
TxRDY pin out = DB buffer empty OR (CTSN = 0) OR (TxEN = 1)
Figure 13: Status Read Format
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