MA808
ADVANCE INFORMATION
DS3162-2.0
MA808
FRAME ALIGNER WITH OPTIONAL TIME SLOT ZERO RECEIVER
The MA808 Frame Aligner chip has been primarily
designed for use in equipment operating at the CCITT
standard of 2048 kbit/s tor 30 channel PCM data signals.
The basic function of the device is to accept a 2048 kbit/s
data signal, whose frame structure conforms to CCITT
recommendation G732 and frame synchronously align it to a
local exchange/system clock.
The frame aligner operation is such that once a
synchronisation sequence, as defined in CCITT
recommendation G732, is received from a distant source
synchronisation is established. Consequently the data stream
is delayed such as to align it to the timing required at the local
source. Once three successive sync. words are received
containing errors, synchronisation is lost. The chip will remain
out of sync. until the synchronising sequence is received.
The device can also, when configured in the ‘enhanced
mode’ perform the additional function of time slot zero
recovery.
A number of facilities are also provided to simplify the
testing of the device and associated system.
T1
RXI
ALM
R
T2
TSZ
RCK
CK
FRS
LCK
T3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
V
DD
T7
T6
T5
T4
NC
NC
NC
M
SA1
RXO2
RXO1
MA
808
18
17
16
15
14
13
DG24
DP24
Figure 1: Basic Mode pin connections - top view.
M tied to V
SS
FEATURES
s
Fabricated in Low Power CMOS
s
Optional Time Slot Zero Receiver
s
Detection of Frame Alignment Signals for 30
Channel PCM Highways Operating at 2048 kbit/s in
Accordance with CCITT Recommendations G732
s
Delay Compensation and Clock Alignment between
the Transmission Line system and the Exchange
s
Compensation of Phase Jitter, Meeting the
Requirements of CCITT
s
Detection and Indication of Loss of Frame Alignment
s
Provision of a Signal for Generation of AIS
s
Slip Compensation
s
Chip Functional Test Facilities
s
TTL Compatible
s
Operating Power Consumption 75mW max.
s
Single + 5V Supply
s
High Latch-up Immunity
s
256 kHz Clock Output
CCR
RXI
ALM
ER
SA
TSZ
RCK
CK
FRS
LCK
Q8N
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
V
DD
Q1S
Q1N
Q3N
Q4N
Q5N
Q6N
Q7N
M
SA1
RXO2
RXO1
MA
808
18
17
16
15
14
13
DG24
DP24
APPLICATIONS
s
Digital Multiplex Equipment
s
Interfaces between PCM Line and Switching Systems
s
Concentrators
Figure 2: Enhanced Mode pin connections - top view.
M tied to V
DD
1
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
