Le79555
Loop Detector
Description
Off-hook threshold
On-hook threshold
Hysteresis
IGK, Ground-key detector threshold
Test Conditions (See Note 1)
R
D
= 35.4 kΩ
R
D
= 35.4 kΩ
R
D
= 35.4 kΩ
R
L
from BX to GND
Active, Standby, and Tip open
5
Min
9.4
8.8
Typ
11.7
10.4
1.3
9
13
Max
14.0
12.0
Data Sheet
Unit
Note
mA
Relay Driver Output
(RINGOUT, RYOUT1, RYOUT2)
Description
On voltage
Off leakage
Zener breakover
Zener On voltage
Test Conditions (See Note 1)
I
OL
= 40 mA
V
OH
= +5 V
I
Z
= 100 µA
I
Z
= 30 mA
6
7.2
8
Min
Typ
+0.3
Max
+0.7
100
Unit
V
µA
V
Note
Figure 1. Relay Driver Schematic
RINGOUT,
RYOUT1, RYOUT2
BGND
1.
2.
a)
b)
3.
4.
5.
6.
7.
Overload level is defined as THD = 1%.
Overload level is defined as THD = 1.5%.
Balance return signal is the signal generated at V
TX
by V
RX
. This specification assumes that the two-wire, AC-load impedance matches
the programmed impedance.
Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
Tested with 0
Ω
source impedance. 2 MΩ is specified for system design only.
Group delay can be greatly reduced by using a Z
T
network such as that shown in
Figure 7.
The network reduces the group delay to less
than 2 µs and increases 2WRL. The effect of group delay on line card performance also may be compensated for by synthesizing complex
impedance with the QLSLAC™ device.
Minimum current level guaranteed not to cause a false loop detect.
Unless otherwise noted, R
L
= 600
Ω.
Also, refer to the Le79555 device test circuit in
Figure 9, on page 16.
8.
11
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
