Le7942B
Data Sheet
TEST CIRCUITS
(TIP)
A
VTX
VTX
(TIP)
A
B
RL
2
RT
SLIC
SLIC
VL
VAB
RT
VAB
RL
AGND
AGND
RL
2
RRX
RRX
VRX
RSN
RSN
(RING)
B
(RING)
IL4-2 = –20 log (VAB / VRX
)
IL2-4 = –20 log (VTX / VAB
)
BRS = 20 log (VTX / VRX
)
A. Two- to Four-Wire Insertion Loss
B. Four- to Two-Wire Insertion Loss and Balance Return Signal
ZD
A
(TIP)
VTX
VTX
(TIP)
A
B
1/ωC << RL
RL
2
RT
S1
C
SLIC
R
R
AGND
VL
RT
S2
VM
AGND
VS
SLIC
VL
ZIN
RL
2
RRX
VRX
RSN
B(RING)
RSN
(RING)
RRX
S2 Open, S1 Closed:
L-T Long. Bal. = 20 log (VAB / VL)
L-4 Long. Bal. = 20 log (VTX / VL)
Note:
ZD is the desired impedance (e.g., the characteristic
impedance of the line).
S2 Closed, S1 Open:
4-L Long. Sig. Gen. = 20 log (VL / VRX
RL = –20 log (2 VM / VS)
)
C. Longitudinal Balance
D. Two-Wire Return Loss Test Circuit
15
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
