Le75282
Data Sheet
Table 9. Operating States: CFG = 0
Operating State
Idle/Talk
Test
Break Switches
Ringing Switches
Test Switches
OFF
RD31
RD21
RD11
OFFx1
ON
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
1
1
1
1
1
1
1
1
ON
OFF
ON
OFF
ON
OFF
ON
OFF
Ringing
Test/Monitor
Idle/Talk
Test/Monitor
Ringing
Test Ringing
All Off
ON
OFF
02
Notes:
1. RD1, RD2, and RD3 data input values are directed to a given channel when the respective LDx logic signal is set to 0. OFFx
is a per-channel control.
2. A 0 on OFFx resets the Le75282 device, the device will remain in the All Off state until OFFx is returned to 1 and the next
LDx signal is applied.
Table 10. Operating States: CFG = 1
Operating State
Idle/Talk
Test
Ringing
All Off
Idle/Talk
Test/Monitor
Ringing
Test Ringing
All Off
Break Switches
Ringing Switches
Test Switches
OFF
RD31
RD21
RD11
OFFx1
ON
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
ON
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
1
1
1
1
1
1
1
1
ON
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
ON
OFF
02
Notes:
1. RD1, RD2, and RD3 data input values are directed to a given channel when the respective LDx logic signal is set to 0. OFFx
and TSDx are per-channel controls.
2. A 0 on OFFx resets the Le75282 device, the device will remain in the All Off state until OFFx is returned to 1 and the next
LDx signal is applied.
A parallel-in/parallel-out data latch is integrated into the Le75282 device. Operation of the data latch is controlled by the LDx pins.
The data inputs to the latch are the P1’-P3’ logic level pins; the output of the data latch respectively is RD1-RD3 used for state
control.
When the LDx control pin for a given channel is at logic 1 or VREF (of an Le79228 SLAC device), changes on the data inputs
will be ignored.
When the LDx control pin for a given channel is at logic 0, the latch is transparent and changes on the data inputs is passed
directly through as state control. Any changes in the data inputs will be reflected in the state of the switches. When the LDx control
pin returns to logic 1 or VREF, the state of the switches becomes latched; that is, the state of the switches will remain until another
logic 0 transition occurs.
Note in Figure 6, on page 16 that the OFFx and TSDx are not tied to the data latch. OFFx and TSDx are not affected by the LD
input. The OFFx and TSDx (in thermal shutdown state) will override the RD1-RD3 state control for that channel.
OFFx pins have internal pull-down resistors which set the Le75282 device into the All Off state at power-up.
CFG is intended to be fixed at VDD or DGND, if CFG switches states when VDD is applied, the change will be recognized by a
given channel after an LD low transition is applied to that channel.
17
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
