Le75181
APPLICATION
Figure 7. Typical LCAS Application, A/C Versions, Idle or Talk State Shown
VBAT
(Reference)
Data Sheet
SW3
R1
SW1
AD
TIP
Crowbar
Protection*
SCR
&
Trip
CKT
SLIC
RING
R2
SW4
SW2
BD
Ring
Generator
Battery
*Contact a
Zarlink
Sales/Application representative for recommendations.
Table 8. Truth Table
INPUT
0
1
Don’t Care
1.
2.
3.
4.
5.
6.
T
SD
1/Float
1
1/Float
1
0
Tip Break Switch
Closed
Open
Open
Ring Break Switch
Closed
Open
Open
Ringing Return Switch
Open
Closed
Open
Ring Switch
Open
3, 6
Closed
4
Open
5
Thermal shutdown mechanism is active with T
SD
floating or HIGH.
Forcing T
SD
to LOW overrides the logic input pins and forces an all OFF state.
Idle/Talk state.
Power ringing state.
All OFF state.
Default power up state.
A parallel in/parallel out data latch is integrated into the Le75181 device. Operation of the data latch is controlled by the logic level
input pin LATCH. The data input to the latch is the INPUT pin of the Le75181 device, and the output of the data latch is an internal
node used for state control.
When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from INPUT, through
the data latch to state control. Any changes in INPUT will be reflected in the state of the switches.
When the LATCH control pin is at logic 1, the data latch is active—the Le75181 device will no longer react to changes at the
INPUT control pin. The state of the switches is now latched; that is, the state of the switches will remain as they were when the
LATCH input transitioned from logic 0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high.
Note that the TSD input is not tied to the data latch. TSD is not affected by the LATCH input. TSD input will override state control
via INPUT and LATCH.
14
Zarlink Semiconductor Inc.
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