SP5654
Test Mode
0
1
2
3
4
P1
0
0
1
1
d
P2
0
0
0
0
1
P3
0
1
0
1
0
Test Mode Description
Charge pump down 170mA
Charge pump up 170mA
Charge pump down 50mA
Charge pump up 50mA
F
COMP
to P2; F
PD
/2 to P3;
Lock output switched to out of lock
condition
Lock output switched to inlock condition
5
d
1
1
These test modes are invoked by taking the clock input below V
EE
d=don‘t care
Table
2 Test
mode options
MODE
18 Bit Data entry
4
3
2
1
0
COMPATIBILITY
19 Bit Data entry
TD6382 plus
4
prescaler
TD6381
TD6382 plus
2
prescaler
TD6382
TD6381 plus
2
prescaler
TD6380 plus
2
prescaler
None
TD6380
None
None
Table
3. Programming compatibilities
CLOCK
ENABLE
18–BIT
DATA ENTRY MSB
2
17
P0
2
16
P1
2
15
P2
2
14
P3
FREQUENCY DATA
19–BIT
DATA ENTRY MSB
2
18
P0
2
17
P1
2
16
P2
2
15
P3
FREQUENCY DATA
t
CE
t
ES
3V
1.5V
t
ES
t
SU
t
HD
t
CE
t
EH
t
LO
t
Hi
=Enable set up time
=Data set up time
=Data hold time
=Clock–to–enable time
=Enable hold time
=Clock low period
=Clock high period
t
LO
t
Hi
t
EH
2
14
2
13
2
2
2
1
2
0
LSB
MSB IS TRANSMITTED
FIRST
2
13
2
12
2
2
2
1
2
0
LSB
CLOCK
ENABLE
3V
1.5V
DATA
3V
1.5V
t
SU
t
HD
Fig. 4 Data format and timing
6
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
