KESTX01
ELECTRICAL CHARACTERISTICS A.C.
T amb = –40°C to + 85°C, V
CC
= 3.5V to 6.5V. These characteristics are guaranteed by either production test, characterisation
or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Parameter
Output current at
fundamental, V
CC
=3.5V
Output current at
Fundamental, V
CC
= 3.5V
Output current
fundamental V
CC
= 6.5V
Output level at 2 x
fundamental see note 1
Output level at 3 x
fundamental and all other
spurii see note 1
Phase detector gain
Extinction ratio
see note 2
VCO gain
TXEN settling time
see note 3
Output sidebands due to
reference frequency
see note 4
30dB rise timeRF envelope
of Data pulse
30dB fall timeRF envelope
of Data pulse
VCO operating frequency
PDG
ER
4.7
40
8
Symbol
Min
IF75
1.4
Value
Typ
2.1
Units
Max
2.8
pk–pk
mA
pk-pk
mA
pk–pk
mA
dBc
I
mod
=75µA, F
o
=434MHz
Conditions
IF150
2.4
3.8
4.9
I
mod
=150µA, F
o
=434MHz
IF150(6V5)
3.0
4.6
5.6
I
mod
=150µA, F
o
=434MHz
–32
I
mod
=150µA, F
o
=434MHz
(1)
I
mod
=150µA, F
o
=434MHz (1)
–11
dBc
9.5
µA/rad
dB
V
CC
= 3.5V
G
VCO
Txe
110
5.0
MHz/V
ms
SB
–40
dBc
I
mod
=150µA, F
o
=434MHz
(1, 4)
T30R
380
ns
T30F
430
ns
400
434
460
MHz
V
CC
= 3.5
Notes:
1. The spurii are specified relative to the fundamental, measured in a 300KHz resolution bandwidth.
2. Extinction ratio is defined as the ratio of the output power SPACE to output power MARK measured at the output
operating fequency.
3. Regulatory issues demand that transmission does not take place until the PLL has acquired lock and the VCO is
operating at its final output frequency. This requirement demands that pin TXEN is set high at least Txe ms prior to the
transmission of any data. This value is dependent on the PLL loop bandwidth and hence on the value of the external
loop filter component values. The specification value above is for the loop filter components shown in the applications
diagram (Figure. 6)
4. Sidebands on the output due to the PLL reference are a function of the PLL loop bandwidth and the application.
Reducing the closed loop bandwidth of the PLL loop will aid in reducing the level of the PLL reference spurii.
3
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
