GP4020
76
50
100
1
25
QPA100
Figure 2 - Pin connections (top view)
Associated
circuit block
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Signal Name
SADD[0]
SADD[1]
SADD[2]
SADD[3]
SADD[4]
SADD[5]
GNDPWR
SADD[6]
SADD[7]
V
DD
PWR
NSCS[0]
NSCS[1]
NSCS[2A]
SADD[19]
SDATA[0]
SDATA[1]
SDATA[2]
SDATA[3]
GNDPWR
SDATA[4]
SDATA[5]
V
DD
PWR
SDATA[6]
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
System Address bit 0
System Address bit 1
System Address bit 2
System Address bit 3
System Address bit 4
System Address bit 5
System Address bit 6
System Address bit 7
System Chip Select 0 - Active Low
System Chip Select 1 - Active Low
System Chip Select 2A - Active Low
System Address bit 19
System Data bit 01
System Data bit 11
System Data bit 21
System Data bit 31
System Data bit 41
System Data bit 51
System Data bit 61
Notes
1
1
1
Cont
…
Table 1 - Pin descriptions
All V
DD
and GND pins must be connected to ensure reliable operation. Any unused input pins must be tied either
high or low; no inputs should be left unconnected.
3
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
