GP4020
Pin No.
60
61
62
63
64
65
66
67
Signal name
GND
SIGN0
MAG0
SAMPCLK
POWER_GOOD
PR_XOUT
PR_XIN
TEST
Type
PWR
I
I
O
I
O
I
I
Associated
circuit block
Description
Notes
CORR
CORR
CORR
PCL
SCG
SCG
Sampled Sign (polarity) data from RF front end.
Sampled Mag (amplitude) data from RF front
end.
Sample Clock output to the RF front end. Provides
a 5·714MHz clock with a 4:3 mark to space ratio.
Power Monitor input, high for normal operation;
low forces the GP4020 into Power Down mode.
System Clock Oscillator - crystal output for 10 to
16MHz crystal.
System Clock Oscillator - crystal inputfor 10 to
16MHz crystal.
TEST select pin,used with TESTMODE (pin 74).
Used for test purposes only and should be
connected to GND in normal operation.
Timemark output. This pin can be used to produce
a UTC-aligned 1 PPS output, or TIC output.
TEST select pin,used with TESTMODE (pin 74).
Used for test purposes only and should be
connected to GND in normal operation.
Real-time Clock Oscillator input for 32kHz crystal.
Real-time Clock Oscillator output for 32kHz crystal.
TEST select pin,used with TEST (pin 67). Used
for test purposes only and should be connected
to GND in normal operation.
System Reset input.
UART 2 Transmit data output.
UART 2 Receive data input.
UART 1 Transmit data output.
UART 1 Receive data input.
GND connection for PLL Block.
V
DD
connection for PLL Block.
5
68
69
70
V
DD
TIMEMARK / TIC
IDDQTEST
PWR
O
I
1PPS
71
72
73
74
GND
RTC_XIN
RTC_XOUT
TESTMODE
PWR
I
O
I
RTC
RTC
5
75
76
77
78
79
80
81
82
83
NSRESET
U2TXD
U2RXD
U1TXD
U1RXD
PLLGND
PLLVDD
GND
PLLAT1
I
O
I
O
I
PWR
PWR
PWR
O
PCL
UART2
UART2
UART1
UART1
SCGPLL
SCGPLL
SCGPLL
3
3
84
85
86
NICE
V
DD
TCK/bdiag[0]/XReq
I
PWR
I/O
JTAG/SSM
MUTIPLEX
JTAG/SSM
System Clock Generator PLL Analog Test I/O.
Reserved for TEST purposes only and should
NOT be connected in normal operation.
ARM7 operating mode and JTAG / SSM Signal
Multiplex (pins 86, 87, 88, 89).
JTAG Test Clock/SSM Diagnostic broadcast
debug output bdiag[0]/System test control input
XReq.
JTAG Test Data In/SSM Diagnostic broadcast
debug output bdiag[1]/System Test control input
X/Write.
JTAG Test Data Out/SSM Diagnostic broadcast
debug output bdiag[2]/System test control input
XBurst.
6
6
87
TDI/bdiag[1]/XWrite
I/O
JTAG/SSM
6
88
TDO/bdiag[2]/XBurst
I/O
JTAG/SSM
6
Table 1 - Pin descriptions (continued)
Cont…
5
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
