GP4020
Electrical Characteristics (continued)
Characteristic
40MHz Low Level Differential Input
Input voltage bias
Differential input voltage
Input differential hysteresis
Input clock frequency
Input capacitance
Power-on delay
Processor Clock Oscillator
Frequency
Start up time
Mark:space
Transconductance
Output impedance
Feedback resistance
Phase Locked Loop
Input frequency
Output frequency
Duty cycle
Phase alignment offset (falling edges
of CLKINB, CLKFBKB)
Phase Alignment Jitter
Phase Jitter
CLKINB to CLKOUTB delay
PLL Settling Time
Real Time Clock
Crystal frequency
Start up time
Transconductance
Output impedance
Feedback resistance
B
µ
ILD Serial Input / Output (BSIO)
3-wire Bus Interface
BSIO_CLK output frequency
Serial clock output low period
Serial clock output high period
Serial clock output rise time
Serial clock output fall time
Serial data output delay
Serial enable output delay
Serial chip select enable to first clock
edge delay
Serial last clock edge delay to chip
select disable
Symbol
Min.
0
100
12
40
5
Value
Typ. Max.
1·715
24
150
150
F
PRXIN
T
PRXSU
g
m
Z
O
R
F
F
PLLIN
F
PLLOUT
10
45
1·0
10
50
2·24
93
220
16
55
4·4
Units
Conditions
V
DBIAS
V
DIFIN
V
DIFHYS
F
DIFIN
C
DIFIN
V
mV
mV
MHz
pF
ns
MHz
ms
%
mA/V
kΩ
kΩ
MHz
MHz
%
ns
ns
ns
ns
µs
kHz
ms
µA/V
MΩ
MΩ
Min. V
DD
= 3·0V Note 1
40MHz from RF front end
Not including package
Correct external components
Across frequency range
Across all conditions
10
10
45
50
20
250
55
+-0·2
+-0·25
+-0·15
Can be divided down by 1,2,4 or
8 for optimal BµlLD_CLK freq.
T
PLLSET
F
RTC
T
RTCSTART
G
MRTC
Z
ORTC
R
FRTC
0·43
147
32·768
400
9·56
422
10
Note 2
Cycle-cycle edge jitter Note 2
In clock bypass mode
In clock synchronisation mode
Correct external components
Across frequency range
External component
F
SEROF
T
SERCL
T
SERCH
T
SERCR
T
SERCF
T
SERDOD
T
SEREOD
T
SERCDC
T
SERCEC
10
40
40
10
10
20
20
-2 0
-2 0
70
70
MHz
ns
ns
ns
ns
ns
ns
ns
ns
SEROUT ref SERCLK
SERSEL ref SERCLK
Cont
…
NOTES
1. The input pair CLK_T, CLK_I may be driven by a low amplitude differential sinewave from an RF Front-end.
Direct DC connection to a GP2010 or GP2015 RF front end is NOT possible, as the maximum DC bias from these
devices is in excess of maximum input bias limit.
2. Jitter is dominated by supply-noise effects. Users must keep on-chip supply noise below 1Vp-p by the use of
low noise outputs and as many supply pins as possible.
13
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
