GP4020
Pin No.
89
Signal name
TMS/bdiag[3]/XCon
Type
I/O
Associated
circuit block
JTAG/SSM
Description
JTAG Test Mode Select/SSM Diagnostic
broadcast debug output bdiag[3]/System test
control input XCon.
JTAG interface Reset or SSM debug interface
multiplex (pins 86, 87, 88 and 89).
General Purpose Input/Output 7. Can be
multiplexed to SCG PLL Digital Test Output
(PLLDT1).
General Purpose Input/Output 6.
General Purpose Input/Output 5. Can be
multiplexed to DISCOP discrete output from
correlator.
General Purpose Input/Output 4. Also directly
connects to DISCIP1 on the 12-channel correlator.
General Purpose Input/Output 3. Can be
multiplexed to BSIO Slave Select[1].
General Purpose Input/Output 2. Can be
multiplexed to BSIO Slave Select[0].
General Purpose Input/Output 1. Can be
multiplexed to BSIO Data Input/Output.
General Purpose Input/Output pin 0. Can be
multiplexed to BSIO_CLK output.
Notes
6
90
91
NTRST
GPI0[7]/PLLDT1
I
I/O
JTAG/SSM
GPIO/SCG PLL
6
3
92
93
GPIO[6]
GPIO[5]/DISCOP
I/O
I/O
GPIO
GPIO/CORR
3
3
94
95
96
97
98
99
100
GND
GPIO[4]/DISCIP1
GPIO[3]/BSIO_SS[1]
GPIO[2]/BSIO_SS[0]
V
DD
GPIO[1]/BSIO_DATA
GPIO[0]/BSIO_CLK
PWR
I/O
I/O
I/O
PWR
I/O
I/O
GPIO/CORR
GPIO/BSIO
GPIO/BSIO
3
3
3
GPIO/BSIO
GPIO/BSIO
3
3
Table 1 - Pin descriptions (continued)
NOTES
1.
High impedance is achieved on pins 11 to 18, 20, 21, 23 to 29, 31, 32, 34 to 37 when either:
(a) Data is not being written from GP4020.
(b) POWER_GOOD (pin 64) is low.
(c) Bit 1 (RF_PD) of POW_CNTL register is high.
(d) Bit 10 (RF_SLEEP) of POW_CNTL register is high.
2.
NSUB (pin 52) is the Upper Byte select output from the Memory Peripheral Controller, when single chip 16-bit
memories with NUB and NLB inputs are used. NSUB maps to NUB and address line SADD[0] to NLB.
3.
Input is tolerant to being driven with a +5V HIGH level, as well as +3·3V HIGH nominal level.
4.
Both CLK_T (pin 58) and CLK_I (pin 59) should not have an external DC bias of GREATER than +1·7V . Direct
connection from a GP2010/GP2015 RF front end is NOT possible, without bias-shift circuit (Figure 3).
5.
TEST (pin 67) and TESTMODE (pin 74) are used together to set up manufacturing test modes for the GP4020,
as shown in Table 2 (0 = GND, 1 = V
DD
).
TEST
(pin 67)
0
1
0
1
TESTMODE
(pin 74)
0
0
1
1
Test function
Normal operation
Firefly Macrocell test mode
Firefly System test mode
UIM logic test mode
Table 2 - Test mode truth table
Details of ALL test modes are covered in section 2.10 of the Zarlink Semiconductor Firefly MF1 Core Design
Manual.
6
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
