GP4020
Universal Asynchronous Receive/Transmit
(UART1 and UART2)
The full duplex asynchronous channels of UART1 and
UART2 provide RS232 type interfaces, which support
an XON/XOFF software protocol. The Receive and
Transmit channels are double buffered. The UARTs
may be polled, or may use an interrupt scheme for
module bus transfers. An internal Baud rate generator
in each UART can provide selectable data rates,
derived from on-chip sources for an Rx/Tx pair.
Directly-triggered DMA transfers with each UART are
also possible without the need for CPU intervention.
Watchdog (WDOG)
The GP4020 Watchdog can be used to detect hardware
or software run-time errors, and reset the system. The
processor is required to reset the watchdog periodically;
failure to do so will result in a chip-wide reset.
Electrical Characteristics
T
AMB
= -40°C to +85°C, V
DD
= +3·0V to +3·6V (+3·3V nominal). The input thresholds and output voltage limits for the
logic signal pins are tested and guaranteed by production test. All other parameters are guaranteed by characterisation
and design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise specified.
Use in conjunction with the GP4020 GPS Baseband Processor Design Manual (DM5280).
Characteristic
Operating voltage range
Battery backup voltage
Supply Current
Full chip
Symbol
Min.
3·0
2·7
Value
Typ. Max.
3·6
Units
V
V
mA
Simulated. Firefly BµlLD_CLK =
30MHz, outputs loaded with
50pF, 12 tracking correlator
channels
Enabled
Disabled
Enabled
Disabled
Disabled
Enabled - F
OUT
= 30MHz,
Mult Factor = 3
Enabled - F
OUT
= 60MHz,
Mult Factor = 6
Enabled - F
OUT
= 1 20MHz,
Mult Factor = 12
Enabled - F
OUT
= 240MHz,
Mult Factor = 24
Conditions
V
BATT
I
DD
100
40MHz low level differential input I
LLDI
Processor clock oscillator
Phase locked loop
I
PRX
<100
I
PLL
2·9
3·4
4·5
6·2
Real time clock
Firefly MF1 microcontroller
Firefly MF1 microcontroller
Operating frequency
I
RTC
I
FMF1
F
BµILD
3·27
0·7
20
4·4
100
0·9
1·0
mA
nA
mA
nA
µA
mA
mA
mA
mA
7·75
µA
mA/MHz
MHz
31·25
Operating frequency
Output capacitance
F
BµILD
20
27.5
50
MHz
pF
Bµild_CLK – external memory
at >1 wait state or internal
memory at 0 wait state.
Bµild_CLK – external memory
access at 0 wait state.
Total external load, all outputs
and I/Os
Cont
…
12
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
