ACE9020
Power Control Circuits
The inputs PD1 and PD2 are used to select the operating
modes as shown below:
PD1
0
1
1
0
PD2
0
0
1
1
Mode
Sleep
Standby
Transmit Set Up
Duplex
All circuits off
Prescaler On
Prescaler, VHF
oscillator on. Upconverter off
All circuits on
determined primarily by the VHF PLL settling time. The power
down inputs can then be set to (0, 1) the full duplex condition.
The intermediate state should also be used during a ‘handoff’
during conversation on an analogue cellular phone, the VHF
PLL continuing to operate while the main UHF PLL changes
channel, the transmit output being disabled. It is also
recommended that the intermediate state is used when going
from duplex (0, 1) to standby (1, 0) modes.
Operating Notes
Good RF layout techniques should be used for this device
to obtain optimum performance and also minimise crosstalk
between circuit blocks. RF supply decoupling should be
provided adjacent to Vcc pins; a value of 27pF is
recommended.
Two external bias resistors are required. A 22kΩ resistor
is connected from BIAS REF (Pin 4) to ground. This sets an
accurate reference current for the chip. An 18k resistor is
connected from RSET TXPA (Pin 8) to ground which controls
the output level of the VHF oscillator and hence the TXPA
output level.
The power down inputs (PD1, PD2) are compatible with
ACE9030 digital outputs (DO5, 6, 7). These modes allow
circuit operation and power consumption to be optimised. The
ACE9020 can be put in sleep mode (0, 0) when the power
consumption is minimal. The standby mode (1, 0) is used
when the phone is in standby (receive only). The prescaler is
operational to maintain the main UHF PLL; all circuitry
associated with transmit functions is turned off.
There is an intermediate transmit set up state (1, 1). This
allows the VHF oscillator and phase locked loop to stabilise
before enabling the upconverter, preventing spurious
transmissions. The time required for this state will be
Figure 4 - Application Diagram
4
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
