54HSC/T630
Control
Cycle
WRITE
READ
READ
READ
S1
Low
Low
High
High
S0
Low
High
High
Low
EDAC Function
Generates Checkword
Read Data BCheckword
Latch & Flag Error
Correct Data Word &
Generate Syndrome Bits
Data UO
Input Data
Input Data
Latch Data
Output
Corrected
Data
Checkword
Output Checkword
Input Checkword
Latch Checkword
Output Syndrome Bits
Error Flags
SEF
Low
Low
Enabled
Enabled
DEF
Low
Low
Enabled
Enabled
Table 1: Control Functions
Total Number of Errors
16-bit Data
0
1
0
1
2
0
6-bit Checkword
0
0
1
1
0
2
SEF
Low
High
High
High
High
High
Error Flags
DEF
Low
Low
Low
High
High
High
Data Correction
Not Applicable
Correctlon
Correction
Interrupt
Interrupt
Interrupt
Table 2: Error Functions
ERROR DETECTION & CORRECTION
During a memory write cycle, six check bits (CBO-CB5)
are generated by eight-input parity generators using the data
bits defined in Table 3. During a memory read cycle, the 6-bit
checkword is retrieved along with the actual data.
Error detection is accomplished as the 6-bit checkword and
the 16-bit data word from memory are applied to internal parity
generators/checkers. If the parity of all six groupings of data
and check bits are correct, it is assumed that no error has
occurred and both error flags will be low. It should be noted
that the sense of two of the check bits, bits CBO and CB1, is
inverted to ensure that the gross-error condition of all lows and
all highs is detected.
If the parity of one or more of the check groups is incorrect,
an error has occurred and the proper error flag or flags will be
set high. Any single error in the 16bit data word will change the
sense of exactly three bits of the 6-bit checkword. Any single
error in the 6bit checkword changes the sense of only that one
bit. In either case, the single error flag will be set high while the
dual error flag will remain low.
Any two-bit error will change the sense of an even number
of check bits. The two-bit error is not correctable since the
parity tree can only identify singlebit errors. Both error flags are
set high when any two-bit error is detected.
Three or more simultaneous bit errors cause the EDAC to
transmit that no error, a correctable error, or an uncorrectable
error has occurred and hence produce erroneous results in all
three cases.
Error correction is accomplished by identifying the bad bit
and inverting it. Identification of the erroneous bit is achieved
by comparing the 16-bit word and 6-bit checkword from
memory with the new checkword with one (checkword error)
or three (data word error) inverted bits.
As the corrected word is made available on the data word l/
O port, the checkword l/O port presents a 6-bit syndrome error
code. This syndrome code can be used to identify the
corrupted bit in memory (see Table 4. overleaf).
2
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
