YMF724F
PIN DESCRIPTION
1. PCI Bus Interface (53-pin)
name
PCICLK
I/O
Type
Size
function
I
P
PCI Clock
Reset
RST#
I
P
AD[31:0]
C/BE[3:0]#
PAR
IO
IO
IO
IO
IO
IO
IO
I
Ptr
Ptr
Ptr
Pstr
Pstr
Pstr
Pstr
P
Address / Data
Command / Byte Enable
Parity
FRAME#
IRDY#
Frame
Initiator Ready
Target Ready
Stop
TRDY#
STOP#
IDSEL
ID Select
DEVSEL#
REQA#
GNTA#
PCREQ#
PCGNT#
PERR#
IO
O
Pstr
P
Device Select
PCI Request
I
P
PCI Grant
O
Ptr
Ptr
Pstr
Pod
Pod
Ptr
PC/PCI Request
PC/PCI Grant
Parity Error
I
IO
O
SERR#
System Error
Interrupt signal output for PCI bus
Serialized IRQ.
INTA#
O
SERIRQ#
IO
2. AC’97 Interface (6-pin)
Name
I/O
Type
Size
function
CRST#
O
O
T
C
6mA
-
Reset signal for AC’97
CMCLK
Master Clock of AC link (24.576MHz) and
AC3F2
CBCLK
CSDO
CSDI
I
O
I
T
T
T
T
-
AC-link: Bit Clock for AC’97 audio data
AC-link: AC’97 Serial audio output data
AC-link: AC’97 Serial audio input data
AC-link: Synchronized signal
6mA
-
CSYNC
O
6mA
January 14, 1999
-4-
YAMAHA [ YAMAHA CORPORATION ]
