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YGV629 参数 Datasheet PDF下载

YGV629图片预览
型号: YGV629
PDF下载: 下载PDF文件 查看货源
内容描述: VC1视频控制器1 [VC1 Video Controller 1]
分类和应用: 控制器
文件页数/大小: 26 页 / 882 K
品牌: YAMAHA [ YAMAHA CORPORATION ]
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YGV629  
Pin Table  
Pin Name  
No. I/O  
Function  
Level  
5Tr Drive  
CPU Interface  
D7-0  
PS2-0  
CS_N  
RD_N  
8
3
1
1
1
1
1
1
1
1
1
1
1
1
I/O CPU Data Bus  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
4mA  
I
I
I
I
CPU Port Selection  
Chip Select  
Read Pulse  
WR_N  
Write Pulse  
WAIT_N  
READY_N  
INT_N  
SER_N  
SCS_N  
SDIN  
SDOUT  
SCLK  
RESET_N  
OT CPU Bus Wait  
OT CPU Bus Ready  
Od Interrupt  
4mA  
4mA  
4mA  
I
I
I
CPU Interface Selection  
Serial Interface Chip Select  
Serial Interface Data Input  
OT Serial Interface Data Output  
4mA  
I
I
Serial Clock Input  
Reset  
Pattern Memory Interface  
MD15-0  
MA24-0  
MOE_N  
MWE_N  
RAHZ_N  
Monitor Interface  
R,G,B  
IREF  
DR5-0  
DG5-0  
DB5-0  
16 I/O Pattern Memory Data Bus  
25 OT Pattern Memory Address Bus  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
4mA  
4mA  
4mA  
4mA  
1
1
1
OT Pattern Memory Output Enable  
OT Pattern Memory Write Pulse  
I
Pattern Memory High Impedance Switching  
3
1
6
6
6
1
O
-
O
O
O
O
Analog Image Output  
Analog  
Analog  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
DAC Reference Power Supply  
Digital Image R Output  
Digital Image G Output  
Digital Image B Output  
Vertical Synchronizing Signal Output  
Horizontal Synchronizing / Composite  
Synchronizing Signal Output  
Vertical Synchronizing Input  
Horizontal Synchronizing Input  
Display Timing Output  
4mA  
4mA  
4mA  
4mA  
VSYNC_N  
HCSYNC_N  
1
O
LVCMOS  
4mA  
VSIN_N  
HSIN_N  
BLANK_N  
FSC  
YS_N  
DOTCLK  
Clock  
1
1
1
1
1
1
I
I
O
O
O
O
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
4mA  
4mA  
4mA  
4mA  
Sub-carrier Clock  
YS Output  
Dot Clock Output  
XIN  
XOUT  
DTCKIN  
DTCKS_N  
FILTER  
PLLCTL5-0  
1
1
1
1
1
6
I
O
I
I
-
Reference Clock Input  
X’tal connection pin  
Display system Clock Input  
Display system Clock Selection  
PLL Filter Connection  
PLL Control  
LVCMOS  
LVCMOS  
Analog  
I
LVCMOS  
Od: open drain output, OT: 3-state output, 5Tr: 5V Tolerant, Drive: driving capability  
Note) VC1 has no built-in pull up resistor. Pull up the pins externally as necessary.  
The tolerant attribute is an attribute of the input buffer, output buffer that can become the high-impedance  
state, and bi-directional buffer, and indicates it can endure the 5V signal.  
-5-  
4GV629A50