R
Spartan-II FPGA Family: Pinout Tables
XC2S100 Device Pinouts (Continued)
XC2S100 Pad
Name
Bndry
Function Bank TQ144 PQ208 FG256 FG456 Scan
I/O
0
0
-
-
P188
P189
P190
P191
P192
P193
-
A6
B7
C10
A9
107
110
-
I/O, VREF
GND
I/O
P12
-
GND*
C8
D7
E7
GND*
B9
0
0
0
0
0
0
-
-
113
116
122
125
128
131
-
I/O
-
-
E10
A8
I/O
I/O
-
-
D9
I/O
P11
P10
P9
-
P194
P195
C7
B6
E9
I/O
A7
VCCINT
VCCO
P196 VCCINT* VCCINT*
0
P197
VCCO
VCCO
-
Bank 0* Bank 0*
GND
I/O
-
P8
P7
P6
-
P198
P199
P200
-
GND*
A5
GND*
B7
-
0
0
0
0
0
0
0
0
134
137
140
143
146
152
155
-
I/O, VREF
I/O
C6
E8
-
D8
I/O
-
P201
-
B5
C7
I/O
-
D6
D7
I/O
-
P202
P203
-
A4
D6
I/O, VREF
VCCO
P5
-
B4
C6
VCCO
VCCO
Bank 0* Bank 0*
GND
I/O
-
-
-
-
GND*
E6
GND*
B5
-
0
0
0
0
0
0
-
P204
-
158
161
164
167
170
176
-
I/O
-
D5
E7
I/O
-
-
-
E6
I/O
P4
-
P205
-
A3
B4
I/O
C5
A3
I/O
P3
P2
P1
P206
P207
P208
B3
C5
TCK
VCCO
C4
C4
0
VCCO
VCCO
-
Bank 0* Bank 0*
VCCO VCCO
Bank 7* Bank 7*
VCCO
7
P144
P208
-
04/18/01
Notes:
1. IRDY and TRDY can only be accessed when using Xilinx PCI
cores.
2. Pads labelled GND*, VCCINT*, VCCO Bank 0*, VCCO Bank 1*,
VCCO Bank 2*, VCCO Bank 3*, VCCO Bank 4*, VCCO Bank 5*,
VCCO Bank 6*, VCCO Bank 7* are internally bonded to
independent ground or power planes within the package.
3. See "VCCO Banks" for details on VCCO banking.
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
85
XILINX [ XILINX, INC ]
