R
Spartan-II FPGA Family: Functional Description
Library Primitives
Using Block RAM Features
The Spartan-II FPGA family provides dedicated blocks of
on-chip, true dual-read/write port synchronous RAM, with
4096 memory cells. Each port of the block RAM memory
can be independently configured as a read/write port, a
read port, a write port, and can be configured to a specific
data width. The block RAM memory offers new capabilities
allowing the FPGA designer to simplify designs.
Figure 31 and Figure 32 show the two generic library block
RAM primitives. Table 11 describes all of the available
primitives for synthesis and simulation.
RAMB4_S#_S#
WEA
ENA
DOA[#:0]
RSTA
CLKA
Operating Modes
ADDRA[#:0]
DIA[#:0]
Block RAM memory supports two operating modes.
•
•
Read Through
Write Back
WEB
ENB
RSTB
Read Through (One Clock Edge)
DOB[#:0]
CLKB
ADDRB[#:0]
DIB[#:0]
The read address is registered on the read port clock edge
and data appears on the output after the RAM access time.
Some memories may place the latch/register at the outputs
depending on the desire to have a faster clock-to-out versus
setup time. This is generally considered to be an inferior
solution since it changes the read operation to an
asynchronous function with the possibility of missing an
address/control line transition during the generation of the
read pulse clock.
DS001_31_061200
Figure 31: Dual-Port Block RAM Memory
RAMB4_S#
WE
EN
RST
CLK
DO[#:0]
Write Back (One Clock Edge)
ADDR[#:0]
DI[#:0]
The write address is registered on the write port clock edge
and the data input is written to the memory and mirrored on
the write port input.
DS001_32_061200
Figure 32: Single-Port Block RAM Memory
Block RAM Characteristics
Table 11: Available Library Primitives
1. All inputs are registered with the port clock and have a
setup to clock timing specification.
Primitive
RAMB4_S1
RAMB4_S1_S1
RAMB4_S1_S2
RAMB4_S1_S4
RAMB4_S1_S8
RAMB4_S1_S16
Port A Width
Port B Width
1
N/A
1
2
4
8
2. All outputs have a read through or write back function
depending on the state of the port WE pin. The outputs
relative to the port clock are available after the
clock-to-out timing specification.
3. The block RAM are true SRAM memories and do not
have a combinatorial path from the address to the
output. The LUT cells in the CLBs are still available with
this function.
16
RAMB4_S2
2
N/A
2
4
8
16
RAMB4_S2_S2
RAMB4_S2_S4
RAMB4_S2_S8
RAMB4_S2_S16
4. The ports are completely independent from each other
(i.e., clocking, control, address, read/write function, and
data width) without arbitration.
5. A write operation requires only one clock edge.
6. A read operation requires only one clock edge.
The output ports are latched with a self timed circuit to
guarantee a glitch free read. The state of the output port will
not change until the port executes another read or write
operation.
DS001-2 (v2.8) June 13, 2008
Product Specification
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