R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (continued)
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan devices and are expressed in nanosec-
onds unless otherwise noted.
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-4
-3
(1)
Symbol
Dual Port RAM
Size
Min Max Min Max Units
Write Operation
T
T
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
8.0
4.0
1.5
0
-
11.6
5.8
2.1
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCDS
WPDS
-
-
T
-
-
ASDS
T
-
-
AHDS
T
T
1.5
0
-
1.6
0
-
DSDS
DHDS
WSDS
WHDS
WODS
-
-
-
-
T
T
T
WE setup time before clock K
WE hold time after clock K
1.5
0
1.6
0
-
-
Data valid after clock K
-
6.5
-
7.0
Notes:
1. Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing
Spartan CLB RAM Synchronous (Edge-Triggered) Write Timing
Single Port
Dual Port
TWPS
TWPDS
WCLK (K)
WCLK (K)
TWSS
TWHS
TWSDS
TWHDS
WE
WE
TDHS
TDHDS
TDSS
TDSDS
DATA IN
DATA IN
TAHS
TASS
TAHDS
TASDS
ADDRESS
DATA OUT
ADDRESS
DATA OUT
TILO
TILO
TILO
TILO
TWODS
OLD
TWOS
OLD
NEW
NEW
DS060_34_011300
46
www.xilinx.com
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
