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Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan series devices achieve high-performance, low-cost
operation through the use of an advanced architecture and
semiconductor technology. Spartan and Spartan-XL
devices provide system clock rates exceeding 80 MHz and
internal performance in excess of 150 MHz. In contrast to
other FPGA devices, the Spartan series offers the most
cost-effective solution while maintaining leading-edge per-
formance. In addition to the conventional benefit of high vol-
ume programmable logic solutions, Spartan series FPGAs
also offer on-chip edge-triggered single-port and dual-port
RAM, clock enables on all flip-flops, fast carry logic, and
many other features.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA.
Configurable Logic Blocks (CLBs)
The CLBs are used to implement most of the logic in an
FPGA. The principal CLB elements are shown in the simpli-
fied block diagram in Figure 2. There are three look-up
tables (LUT) which are used as logic function generators,
two flip-flops and two groups of signal steering multiplexers.
There are also some more advanced features provided by
the CLB which will be covered in the Advanced Features
Description, page 13.
The Spartan/XL families leverage the highly successful
XC4000 architecture with many of that family’s features and
benefits. Technology advancements have been derived
from the XC4000XLA process developments.
Function Generators
Two 16 x 1 memory look-up tables (F-LUT and G-LUT) are
used to implement 4-input function generators, each offer-
ing unrestricted logic implementation of any Boolean func-
tion of up to four independent input signals (F1 to F4 or G1
to G4). Using memory look-up tables the propagation delay
is independent of the function implemented.
Logic Functional Description
The Spartan series uses a standard FPGA structure as
shown in Figure 1, page 2. The FPGA consists of an array
of configurable logic blocks (CLBs) placed in a matrix of
routing channels. The input and output of signals is
achieved through a set of input/output blocks (IOBs) forming
a ring around the CLBs and routing channels.
A third 3-input function generator (H-LUT) can implement
any Boolean function of its three inputs. Two of these inputs
are controlled by programmable multiplexers (see box "A" of
Figure 2). These inputs can come from the F-LUT or G-LUT
outputs or from CLB inputs. The third input always comes
from a CLB input. The CLB can, therefore, implement cer-
tain functions of up to nine inputs, like parity checking. The
three LUTs in the CLB can also be combined to do any arbi-
trarily defined Boolean function of five inputs.
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•
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CLBs provide the functional elements for implementing
the user’s logic.
IOBs provide the interface between the package pins
and internal signal lines.
Routing channels provide paths to interconnect the
inputs and outputs of the CLBs and IOBs.
DS060 (v1.6) September 19, 2001
Product Specification
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