R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL V Clamping
Table 4: Supported Sources for Spartan/XL Inputs
CC
Spartan-XL FPGAs have an optional clamping diode con-
Spartan
Inputs
Spartan-XL
nected from each I/O to V . When enabled they clamp
CC
Inputs
ringing transients back to the 3.3V supply rail. This clamping
3.3V
action is required in 3.3V PCI applications. V
a global option affecting all I/O pins.
clamping is
5V,
5V,
CC
Source
TTL CMOS
CMOS
Spartan-XL devices are fully 5V TTL I/O compatible if V
Any device, V = 3.3V,
CC
√
√
√
√
Unreli-
able
Data
√
√
√
CC
clamping is not enabled. With V
clamping enabled, the
CMOS outputs
CC
Spartan-XL devices will begin to clamp input voltages to
Spartan family, V = 5V,
CC
one diode voltage drop above V . If enabled, TTL I/O com-
CC
TTL outputs
patibility is maintained but full 5V I/O tolerance is sacrificed.
The user may select either 5V tolerance (default) or 3.3V
PCI compatibility. In both cases negative voltage is clamped
to one diode voltage drop below ground.
Any device, V = 5V,
CC
TTL outputs (V ≤ 3.7V)
OH
Any device, V = 5V,
√
√ (default
mode)
CC
CMOS outputs
Spartan-XL devices are compatible with TTL, LVTTL, PCI
3V, PCI 5V and LVCMOS signalling. The various standards
are illustrated in Table 5.
Table 5: I/O Standards Supported by Spartan-XL FPGAs
Signaling
Standard
VCC
Clamping
Output
Drive
V
V
V
V
V
OL MAX
IH MAX
IH MIN
IL MAX
OH MIN
TTL
LVTTL
Not allowed
OK
12/24 mA
12/24 mA
24 mA
5.5
2.0
0.8
2.4
0.4
3.6
5.5
3.6
3.6
2.0
2.0
0.8
0.8
2.4
2.4
0.4
0.4
PCI5V
Not allowed
Required
OK
PCI3V
12 mA
50% of V
50% of V
30% of V
30% of V
90% of V
10% of V
10% of V
CC
CC
CC
CC
CC
CC
CC
CC
LVCMOS 3V
12/24 mA
90% of V
Additional Fast Capture Input Latch (Spartan-XL only)
Table 6: Output Flip-Flop Functionality
The Spartan-XL IOB has an additional optional latch on the
input. This latch is clocked by the clock used for the output
flip-flop rather than the input clock. Therefore, two different
clocks can be used to clock the two input storage elements.
This additional latch allows the fast capture of input data,
which is then synchronized to the internal clock by the IOB
flip-flop or latch.
Clock
Clock Enable
Mode
T
D
Q
Power-Up
or GSR
X
X
0*
X
SR
Flip-Flop
X
0
1*
X
0*
0*
1
X
D
X
X
Q
D
Z
To place the Fast Capture latch in a design, use one of the
special library symbols, ILFFX or ILFLX. ILFFX is a trans-
parent-Low Fast Capture latch followed by an active High
input flip-flop. ILFLX is a transparent Low Fast Capture latch
followed by a transparent High input latch. Any of the clock
inputs can be inverted before driving the library element,
and the inverter is absorbed into the IOB.
X
0
X
0*
Q
Legend:
X
Don’t care
Rising edge (clock not inverted).
SR
0*
1*
Z
Set or Reset value. Reset is default.
IOB Output Signal Path
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
3-state
Output signals can be optionally inverted within the IOB,
and can pass directly to the output buffer or be stored in an
edge-triggered flip-flop and then to the output buffer. The
functionality of this flip-flop is shown in Table 6.
8
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DS060 (v1.6) September 19, 2001
Product Specification
XILINX [ XILINX, INC ]
