R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 12: Boundary Scan Instructions
Instruction
Test
TDO.T
TDO.O
I/O Data
Source
Bit 0 ( TDO end)
Bit 1
Bit 2
TDO
Source
I2
0
I1
0
I0
0
Selected
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
EXTEST
DR
DR
0
0
1
SAMPLE/
DR
Pin/Logic
PRELOAD
0
0
1
1
1
0
0
1
0
USER 1
USER 2
BSCAN.
TDO1
User Logic
User Logic
Pin/Logic
MODE.I
BSCAN.
TDO2
Bottom-edge IOBs (Left to Right)
READBACK
CONFIGURE
Readback
Data
Right-edge IOBs (Bottom to Top)
BSCANT.UPD
1
1
0
1
1
0
DOUT
Disabled
-
(TDI end)
IDCODE
(Spartan-XL
only)
IDCODE
Register
DS060_21_080400
Figure 21: Boundary Scan Bit Sequence
1
1
1
BYPASS
Bypass
-
Register
BSDL (Boundary Scan Description Language) files for
Spartan/XL devices are available on the Xilinx website in
the File Download area. Note that the 5V Spartan devices
and 3V Spartan-XL devices have different BSDL files.
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-state. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
Including Boundary Scan in a Design
If boundary scan is only to be used during configuration, no
special schematic elements need be included in the sche-
matic or HDL code. In this case, the special boundary scan
pins TDI, TMS, TCK and TDO can be used for user func-
tions after configuration.
The first two bits in the I/O data register are TDO.T and
TDO.O, which can be used for the capture of internal sig-
nals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by
Xilinx for internal testing.
To indicate that boundary scan remain enabled after config-
uration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in Figure 22.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 21.
The device-specific pinout tables for the Spartan/XL devices
include the boundary scan locations for each IOB pin.
Optional
To User
Logic
IBUF
BSCAN
TDI
TMS
TCK
TDI
TDO
DRCK
IDLE
TDO
TMS
TCK
To User
Logic
TDO1
TDO2
SEL1
SEL2
From
User Logic
DS060_22_080400
Figure 22: Boundary Scan Schematic Example
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
23
XILINX [ XILINX, INC ]
