R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
inverted with respect to the sense of the flip-flop clock
inputs. Consequently, within the same CLB, data at the
RAMs SPO line can be stored in a flip-flop with either the
same or the inverse clock polarity used to write data to the
RAM.
TWPS
WCLK (K)
WE
TWHS
TDHS
TAHS
TWSS
The WE input is active High and cannot be inverted within
the CLB.
Allowing for settling time, the data on the SPO output
reflects the contents of the RAM location currently
addressed. When the address changes, following the asyn-
TDSS
DATA IN
chronous delay T , the data stored at the new address
ILO
TASS
location will appear on SPO. If the data at a particular RAM
address is overwritten, after the delay T
will appear on SPO.
, the new data
WOS
ADDRESS
Dual-Port Mode
TILO
TILO
In dual-port mode, the function generators (F-LUT and
G-LUT) are used to create a 16 x 1 dual-port memory. Of
the two data ports available, one permits read and write
operations at the address specified by A[3:0] while the sec-
ond provides only for read operations at the address speci-
fied independently by DPRA[3:0]. As a result, simultaneous
read/write operations at different addresses (or even at the
same address) are supported.
TWOS
DATA OUT
OLD
NEW
DS060_13_080400
Figure 13: Data Write and Access Timing for RAM
WCLK can be configured as active on either the rising edge
(default) or the falling edge. While the WCLK input to the
RAM accepts the same signal as the clock input to the asso-
ciated CLB’s flip-flops, the sense of this WCLK input can be
The functional organization of the 16 x 1 dual-port RAM is
shown in Figure 14. The dual-port RAM signals and the
4
16 x 1
RAM
4
4
A[3:0]
WE
D
WRITE
CONTROL
READ
OUT
SPO
WCLK
16 x 1
RAM
4
DPRA[3:0]
WRITE
CONTROL
READ
OUT
DPO
DS060_14_043001
Figure 14: Logic Diagram for the Dual-Port RAM
DS060 (v1.6) September 19, 2001
www.xilinx.com
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Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
