R
Spartan and Spartan-XL FPGA Families Data Sheet
IOB
IOB
IOB
IOB
locals
locals
locals
BUFGS
PGCK1
SGCK1
locals
BUFGP
SGCK4
PGCK4
4
BUFGP
4
IOB
locals
X4
locals
IOB
Any BUFGS
One BUFGP
per Global Line
locals
BUFGS
CLB
CLB
locals
CLB
CLB
4
BUFGS
locals
4
IOB
Any BUFGS
One BUFGP
per Global Line
locals
BUFGP
locals
X4
locals
IOB
X4
X4
PGCK2
locals
locals
locals
SGCK3
BUFGP
locals
SGCK2
PGCK3
BUFGS
IOB
IOB
IOB
IOB
ds060_11_080400
Figure 11:
5V Spartan Family Global Net Distribution
The four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to poten-
tially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs. The eight Global Low-Skew
buffers in the Spartan-XL devices combine short delay, neg-
ligible skew, and flexibility.
The Primary Global buffers must be driven by the semi-ded-
icated pads (PGCK1-4). The Secondary Global buffers can
be sourced by either semi-dedicated pads (SGCK1-4) or
internal nets. Each corner of the device has one Primary
buffer and one Secondary buffer. The Spartan-XL family
has eight global low-skew buffers, two in each corner. All
can be sourced by either semi-dedicated pads (GCK1-8) or
internal nets.
Using the library symbol called BUFG results in the software
choosing the appropriate clock buffer, based on the timing
requirements of the design. A global buffer should be spec-
ified for all timing-sensitive global signal distribution. To use
a global buffer, place a BUFGP (primary buffer), BUFGS
(secondary buffer), BUFGLS (Spartan-XL family global
low-skew buffer), or BUFG (any buffer type) element in a
schematic or in HDL code.
Advanced Features Description
Distributed RAM
Optional modes for each CLB allow the function generators
(F-LUT and G-LUT) to be used as Random Access Memory
(RAM).
Read and write operations are significantly faster for this
on-chip RAM than for off-chip implementations. This speed
advantage is due to the relatively short signal propagation
delays within the FPGA.
Memory Configuration Overview
There are two available memory configuration modes: sin-
gle-port RAM and dual-port RAM. For both these modes,
write operations are synchronous (edge-triggered), while
read operations are asynchronous. In the single-port mode,
a single CLB can be configured as either a 16 x 1, (16 x 1)
x 2, or 32 x 1 RAM array. In the dual-port mode, a single
CLB can be configured only as one 16 x 1 RAM array. The
different CLB memory configurations are summarized in
Table 8.
Any of these possibilities can be individually pro-
grammed into a Spartan/XL FPGA CLB.
Table 8:
CLB Memory Configurations
Mode
16 x 1
(16 x 1) x 2
32 x 1
Single-Port
Dual-Port
√
√
√
−
√
−
DS060 (v1.8) June 26, 2008
Product Specification
13
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