R
Platform Flash In-System Programmable Configuration PROMS
XCFxxP PROM as Configuration Master with Internal Oscillator as Clock Source
CE
T
HCE
T
HOE
OE/RESET
CLKOUT
T
CEC
T
T
HB
SB
T
T
T
DDC
T
CDD
COH
OEC
T
T
CECF
OECF
BUSY
T
OE
(optional)
T
CE
DATA
T
CF
T
EOH
T
CFC
HXT
T
DF
T
HCF
CF
EN_EXT_SEL
REV_SEL[1:0]
T
T
T
T
HXT
SXT
SXT
T
T
T
T
HRV
SRV
HRV
SRV
Note: 8 CLKOUT cycles are output after CE rising edge, before CLKOUT
tristates, if OE/RESET remains high, and terminal count has not been reached.
ds123_26_122905
XCF08P, XCF16P,
XCF32P
Symbol
Description
Units
300
Min
Max
CF hold time to guarantee design revision selection is sampled
when VCCO = 3.3V or 2.5V(12)
300
THCF
CF hold time to guarantee design revision selection is sampled
when VCCO = 1.8V(12)
300
300
CF to data delay when VCCO = 3.3V or 2.5V
CF to data delay when VCCO = 1.8V
–
–
–
–
–
–
5
5
–
–
–
–
–
–
TBD
TBD
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCF
OE/RESET to data delay(6) when VCCO = 3.3V or 2.5V
OE/RESET to data delay(6) when VCCO = 1.8V
CE to data delay(5) when VCCO = 3.3V or 2.5V
CE to data delay(5) when VCCO = 1.8V
TOE
25
25
TCE
25
Data hold from CE, OE/RESET, or CF when VCCO = 3.3V or 2.5V
Data hold from CE, OE/RESET, or CF when VCCO = 1.8V
–
TEOH
–
CE or OE/RESET to data float delay(2) when VCCO = 3.3V or 2.5V
CE or OE/RESET to data float delay(2) when VCCO = 1.8V
OE/RESET to CLKOUT float delay(2) when VCCO = 3.3V or 2.5V
OE/RESET to CLKOUT float delay(2) when VCCO = 1.8V
CE to CLKOUT float delay(2) when VCCO = 3.3V or 2.5V
CE to CLKOUT float delay(2) when VCCO = 1.8V
45
TDF
45
TBD
TBD
TBD
TBD
–
TOECF
TCECF
THCE
CE hold time (guarantees counters are reset)(5) when VCCO = 3.3V or 2.5V
CE hold time (guarantees counters are reset)(5) when VCCO = 1.8V
2000
2000
–
DS123 (v2.9) May 09, 2006
www.xilinx.com
33
XILINX [ XILINX, INC ]
