R
Platform Flash In-System Programmable Configuration PROMS
pins a short time before each rising edge of the FPGA's
internally generated CCLK signal. If BUSY is asserted
(High) by the FPGA, the configuration data must be held
until BUSY goes Low. An external data source or external
pull-down resistors must be used to enable the FPGA's
active Low Chip Select (CS or CS_B) and Write (WRITE or
RDWR_B) signals to enable the FPGA's SelectMAP config-
uration process.
data, synchronized by an externally supplied configuration
clock (CCLK). Upon power-up or reconfiguration, the
FPGA's mode select pins are used to select the Slave
SelectMAP configuration mode. The configuration interface
typically requires a parallel data bus, a clock line, and two
control lines (INIT and DONE). In addition, the FPGA’s Chip
Select, Write, and BUSY pins must be correctly controlled to
enable SelectMAP configuration. The configuration data is
read from the PROM byte by byte on pins [D0..D7],
accessed via the PROM's internal address counter which is
incremented on every valid rising edge of CCLK. The bit-
stream data must be set up at the FPGA’s [D0..D7] input
pins a short time before each rising edge of the provided
CCLK. If BUSY is asserted (High) by the FPGA, the config-
uration data must be held until BUSY goes Low. An external
data source or external pull-down resistors must be used to
enable the FPGA's active Low Chip Select (CS or CS_B)
and Write (WRITE or RDWR_B) signals to enable the
FPGA's SelectMAP configuration process.
The Master SelectMAP configuration interface is clocked by
the FPGA’s internal oscillator. Typically, a wide range of fre-
quencies can be selected for the internally generated CCLK
which always starts at a slow default frequency. The FPGA’s
bitstream contains configuration bits which can switch
CCLK to a higher frequency for the remainder of the Master
SelectMAP configuration sequence. The desired CCLK fre-
quency is selected during bitstream generation.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained using the persist option.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained using the persist option.
Connecting the FPGA device to the configuration PROM for
Master SelectMAP (Parallel) Configuration Mode
(Figure 11):
Connecting the FPGA device to the configuration PROM for
•
•
•
•
The DATA outputs of the PROM(s) drive the [D0..D7]
input of the lead FPGA device.
Slave
SelectMAP
(Parallel)
Configuration
Mode
(Figure 12):
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s)
•
•
•
•
The DATA outputs of the PROM(s) drives the [D0..D7]
inputs of the lead FPGA device.
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The PROM CLKOUT (for XCFxxP only) or an external
clock source drives the FPGA's CCLK input
The OE/RESET pins of all PROMs are connected to
the INIT_B pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration.
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The OE/RESET pins of all PROMs are connected to
the INIT_B pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration.
•
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary ICC
•
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary ICC
active supply current (DC Characteristics Over
Operating Conditions).
•
•
For high-frequency parallel configuration, the BUSY
pins of all PROMs are connected to the FPGA's BUSY
output. This connection assures that the next data
transition for the PROM is delayed until the FPGA is
ready for the next configuration data byte.
active supply current (DC Characteristics Over
Operating Conditions).
•
•
For high-frequency parallel configuration, the BUSY
pins of all PROMs are connected to the FPGA's BUSY
output. This connection assures that the next data
transition for the PROM is delayed until the FPGA is
ready for the next configuration data byte.
The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
The PROM CF pin is typically connected to the FPGA's
(1)
FPGA Slave SelectMAP (Parallel) Mode
1. The Slave SelectMAP (Parallel) FPGA configuration mode is sup-
ported only by the XCFxxP Platform Flash PROMs.This mode is
not supported by the XCFxxS Platform Flash PROM.
In Slave SelectMAP mode, byte-wide data is written into the
FPGA, typically with a BUSY flag controlling the flow of
DS123 (v2.6) March 14, 2005
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12
Preliminary Product Specification
XILINX [ XILINX, INC ]
