R
Platform Flash In-System Programmable Configuration PROMs
Standby Mode
The PROM enters a low-power standby mode whenever CE is
deasserted (High). In standby mode, the address counter is
reset, CEO is driven High, and the remaining outputs are
placed in a high-impedance state regardless of the state of the
OE/RESET input. For the device to remain in the low-power
standby mode, the JTAG pins TMS, TDI, and TDO must not be
pulled Low, and TCK must be stopped (High or Low).
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
external pull-up resistor should be used. Typically a 330Ω
Table 10:
Truth Table for XCFxxS PROM Control Inputs
Control Inputs
OE/RESET
High
Low
X
(1)
Notes:
1.
2.
X = don’t care.
TC = Terminal Count = highest address value.
pull-up resistor is used, but refer to the appropriate FPGA
data sheet for the recommended DONE pin pull-up value. If
the DONE circuit is connected to an LED to indicate FPGA
configuration is complete, and is also connected to the
PROM CE pin to enable low-power standby mode, then an
external buffer should be used to drive the LED circuit to
ensure valid transitions on the PROM’s CE pin. If low-power
standby mode is not required for the PROM, then the CE pin
should be connected to ground.
CE
Low
Low
High
Internal Address
If address
<
TC
(2)
: increment
If address
=
TC
(2)
: don't change
Held reset
Held reset
Outputs
DATA
Active
High-Z
High-Z
High-Z
CEO
High
Low
High
High
ICC
Active
Reduced
Active
Standby
Table 11:
Truth Table for XCFxxP PROM Control Inputs
Control Inputs
OE/RESET
CE
CF
BUSY
(5)
Internal Address
If address
<
TC
(2)
and
address
<
EA
(3)
: increment
High
Low
High
Low
If address
<
TC
(2)
and
address
=
EA
(3)
: don't change
Else
If address
=
TC
(2)
: don't change
High
High
Low
X
Notes:
1.
2.
3.
4.
5.
X = don’t care.
TC = Terminal Count = highest address value.
For the XCFxxP with Design Revisioning enabled, EA = end address (last address in the selected design revision).
For the XCFxxP with Design Revisioning enabled, Reset = address reset to the beginning address of the selected bank. If Design
Revisioning is not enabled, then Reset = address reset to address 0.
The BUSY input is only enabled when the XCFxxP is programmed for parallel data output and decompression is not enabled.
Outputs
DATA
Active
High-Z
High-Z
Active and
Unchanged
Active
High-Z
High-Z
CEO
High
High
Low
High
High
High
High
CLKOUT
Active
High-Z
High-Z
Active
Active
High-Z
High-Z
ICC
Active
Reduced
Reduced
Active
Active
Active
Standby
Low
Low
Low
High
High
↑
X
X
High
X
(1)
X
X
Unchanged
Reset
(4)
Held reset
(4)
Held reset
(4)
DS123 (v2.17) October 26, 2009
Product Specification
12
XILINX [ XILINX, INC ]
