R
Platform Flash In-System Programmable Configuration PROMS
T
CKMIN
TCK
TMS
T
T
MSS
MSH
T
T
DIH
DIS
TDI
T
DOV
TDO
DS026_04_020300
Figure 4: Test Access Port Timing
TAP AC Parameters
Table 10 shows the timing parameters for the TAP waveforms shown in Figure 4.
Table 10: Test Access Port Timing Parameters
Symbol
TCKMIN
Description
TCK minimum clock period when VCCJ = 2.5V or 3.3V
TMS setup time when VCCJ = 2.5V or 3.3V
TMS hold time when VCCJ = 2.5V or 3.3V
TDI setup time when VCCJ = 2.5V or 3.3V
TDI hold time when VCCJ = 2.5V or 3.3V
TDO valid delay when VCCJ = 2.5V or 3.3V
Min
100
10
25
10
25
–
Max
–
Units
ns
TMSS
TMSH
TDIS
–
ns
–
ns
–
ns
TDIH
–
ns
TDOV
30
ns
The CLKOUT signal is enabled during programming, and is
active when CE is Low and OE/RESET is High. On CE
rising edge transition, if OE/RESET is High and the PROM
terminal count has not been reached, then CLKOUT
remains active for an additional eights clock cycles before
being disabled. On a OE/RESET falling edge transition,
CLKOUT is immediately disabled. When disabled, the
CLKOUT pin is put into a high-impedance state and should
be pulled High externally to provide a known state.
Additional Features for the XCFxxP
Internal Oscillator
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include
an optional internal oscillator which can be used to drive the
CLKOUT and DATA pins on FPGA configuration interface.
The internal oscillator can be enabled when programming
the PROM, and the oscillator can be set to either the default
frequency or to a slower frequency ("XCFxxP PROM as
Configuration Master with Internal Oscillator as Clock
Source," page 33).
When cascading Platform Flash PROMs with CLKOUT
enabled, after completing it's data transfer, the first PROM
disables CLKOUT and drives the CEO pin enabling the next
PROM in the PROM chain. The next PROM will begin
driving the CLKOUT signal once that PROM is enabled and
data is available for transfer.
CLKOUT
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include
the programmable option to enable the CLKOUT signal
which allows the PROM to provide a source synchronous
clock aligned to the data on the configuration interface. The
CLKOUT signal is derived from one of two clock sources: the
CLK input pin or the internal oscillator. The input clock source
is selected during the PROM programming sequence.
Output data is available on the rising edge of CLKOUT.
During high-speed parallel configuration without
compression, the FPGA drives the BUSY signal on the
configuration interface. When BUSY is asserted High, the
PROMs internal address counter stops incrementing, and
the current data value is held on the data outputs. While
BUSY is High, the PROM will continue driving the CLKOUT
signal to the FPGA, clocking the FPGA’s configuration logic.
DS123 (v2.9) May 09, 2006
www.xilinx.com
8
XILINX [ XILINX, INC ]
