XC9572 In-System Programmable CPLD
Internal Timing Parameters
XC9572-7
XC9572-10
XC9572-15
Symbol
Parameter
Units
Min Max Min Max Min Max
Buffer Delays
t
t
t
t
t
t
Input buffer delay
GCK buffer delay
2.5
1.5
4.5
5.5
2.5
0.0
3.5
2.5
6.0
6.0
3.0
0.0
4.5
3.0
ns
ns
ns
ns
ns
ns
IN
GCK
GSR
GTS
OUT
EN
GSR buffer delay
7.5
GTS buffer delay
11.0
4.5
Output buffer delay
Output buffer enable/disable delay
0.0
Product Term Control Delays
t
t
t
Product term clock delay
Product term set/reset delay
Product term 3-state delay
3.0
2.0
4.5
3.0
2.5
3.5
2.5
3.0
5.0
ns
ns
ns
PTCK
PTSR
PTTS
Internal Register and Combinatorial delays
t
t
t
t
t
t
t
Combinatorial logic propagation delay
Register setup time
0.5
1.0
3.0
ns
ns
ns
ns
ns
ns
ns
ns
PDI
SUI
HI
1.5
3.0
2.5
3.5
3.5
4.5
Register hold time
Register clock to output valid time
Register async. S/R to output delay
0.5
6.5
0.5
7.0
0.5
8.0
COI
AOI
RAI
LOGI
Register async. S/R recovery before clock 7.5
Internal logic delay
10.0
10.0
2.0
2.5
3.0
tLOGILP
Internal low power logic delay
10.0
11.0
11.5
Feedback Delays
t
t
FastCONNECT matrix feedback delay
Function Block local feeback delay
8.0
4.0
9.5
3.5
11.0
3.5
ns
ns
F
LF
Time Adders
3
t
t
Incremental Product Term Allocator delay
Slew-rate limited delay
1.0
4.0
1.0
4.5
1.0
5.0
ns
ns
PTA
SLEW
Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet.
December 4, 1998 (Version 3.0)
5
XILINX [ XILINX, INC ]
