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XC9572-15TQ100C 参数 Datasheet PDF下载

XC9572-15TQ100C图片预览
型号: XC9572-15TQ100C
PDF下载: 下载PDF文件 查看货源
内容描述: XC9572在系统可编程CPLD [XC9572 In-System Programmable CPLD]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 8 页 / 67 K
品牌: XILINX [ XILINX, INC ]
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1
XC9572 In-System Programmable  
CPLD  
1
1*  
December 4, 1998 (Version 3.0)  
Product Specification  
Features  
Power Management  
7.5 ns pin-to-pin logic delays on all pins  
to 125 MHz  
Power dissipation can be reduced in the XC9572 by config-  
uring macrocells to standard or low-power modes of opera-  
tion. Unused macrocells are turned off to minimize power  
dissipation.  
f
CNT  
72 macrocells with 1,600 usable gates  
Up to 72 user I/O pins  
5 V in-system programmable (ISP)  
Operating current for each design can be approximated for  
specific operating conditions using the following equation:  
-
-
Endurance of 10,000 program/erase cycles  
Program/erase over full commercial voltage and  
temperature range  
I
(mA) =  
CC  
MC  
Enhanced pin-locking architecture  
Flexible 36V18 Function Block  
(1.7) + MC (0.9) + MC (0.006 mA/MHz) f  
HP LP  
Where:  
-
90 product terms drive any or all of 18 macrocells  
within Function Block  
MC  
= Macrocells in high-performance mode  
HP  
-
Global and product term clocks, output enables, set  
and reset signals  
MC = Macrocells in low-power mode  
LP  
MC = Total number of macrocells used  
f = Clock frequency (MHz)  
Extensive IEEE Std 1149.1 boundary-scan (JTAG)  
support  
Programmable power reduction mode in each  
macrocell  
Figure 1 shows a typical calculation for the XC9572 device.  
Slew rate control on individual outputs  
User programmable ground pin capability  
Extended pattern security features for design protection  
High-drive 24 mA outputs  
200  
3.3 V or 5 V I/O capability  
Advanced CMOS 5V FastFLASH technology  
Supports parallel programming of more than one  
XC9500 concurrently  
Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP  
and 100-pin TQFP packages  
(160)  
(125)  
100  
(100)  
Description  
(65)  
The XC9572 is a high-performance CPLD providing  
advanced in-system programming and test capabilities for  
general purpose logic integration. It is comprised of four  
36V18 Function Blocks, providing 1,600 usable gates with  
propagation delays of 7.5 ns. See Figure 2 for the architec-  
ture overview.  
0
50  
100  
Clock Frequency (MHz)  
Figure 1: Typical ICC vs. Frequency for XC9572  
December 4, 1998 (Version 3.0)  
1