R
XC95288XV High-Performance CPLD
V
TEST
R
1
Output Type
V
V
R
R
C
L
CCIO
TEST
1
2
Device Output
3.3V
2.5V
1.8V
3.3V
2.5V
320Ω
250Ω
360Ω
660Ω
35 pF
35 pF
R
C
L
2
DS052_03_041200
Figure 3: AC Load Circuit
Internal Timing Parameters
XC95288XV-5
XC95288XV-7 XC95288XV-10
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
Buffer Delays
T
T
T
T
T
T
Input buffer delay
-
-
-
-
-
-
2.0
1.2
2.0
4.0
2.1
0
-
-
-
-
-
-
2.3
1.5
3.1
5.0
2.5
0
-
-
-
-
-
-
3.5
1.8
4.5
7.0
3.0
0
ns
ns
ns
ns
ns
ns
IN
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
GCK
GSR
GTS
OUT
EN
Output buffer enable/disable delay
Product Term Control Delays
T
T
T
Product term clock delay
Product term set/reset delay
Product term 3-state delay
-
-
-
1.7
0.7
5.0
-
-
-
2.4
1.4
7.2
-
-
-
2.7
1.8
7.5
ns
ns
ns
PTCK
PTSR
PTTS
Internal Register and Combinatorial Delays
T
T
T
T
T
T
Combinatorial logic propagation delay
Register setup time
-
2.0
1.5
2.0
1.5
-
0.2
-
2.6
2.2
2.6
2.2
-
1.3
-
3.0
3.5
3.0
3.5
-
1.7
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PDI
-
-
-
-
SUI
Register hold time
-
HI
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
-
-
-
ECSU
ECHO
COI
-
-
-
0.2
5.9
0.5
6.4
1.0
7.0
-
T
-
-
-
AOI
T
5.0
-
7.5
-
10.0
-
RAI
T
T
0.7
5.7
1.4
6.4
1.8
7.3
LOGI
LOGILP
Internal low power logic delay
-
-
-
Feedback Delays
FastCONNECT II feedback delay
Time Adders
T
-
1.6
-
3.5
-
4.2
ns
F
T
T
T
Incremental product term allocator delay
Adjacent macrocell p-term allocator delay
Slew-rate limited delay
-
-
-
0.7
0.3
3.0
-
-
-
0.8
0.3
4.0
-
-
-
1.0
0.4
4.5
ns
ns
ns
PTA
PTA2
SLEW
Advance Information
Preliminary Information
Notes:
1. Please contact Xilinx for up-to-date information on advance specifications.
DS050 (v2.2) August 27, 2001
www.xilinx.com
5
Advance Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
