XC95108 In-System Programmable CPLD
V
TEST
R
1
Output Type
V
V
R
R
C
L
CCIO
TEST
1
2
Device Output
5.0 V
3.3 V
5.0 V
3.3 V
160 Ω
260 Ω
120 Ω
360 Ω
35 pF
35 pF
R
C
L
2
X5906
Figure 3: AC Load Circuit
Internal Timing Parameters
XC95108-7 XC95108-10 XC95108-15 XC95108-20
Min Max Min Max Min Max Min Max
Symbol
Parameter
Units
Buffer Delays
t
t
t
t
t
t
Input buffer delay
2.5
1.5
4.5
5.5
2.5
0.0
3.5
2.5
6.0
6.0
3.0
0.0
4.5
3.0
6.5
3.0
9.5
ns
ns
ns
ns
ns
ns
IN
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
GCK
GSR
GTS
OUT
EN
7.5
11.0
4.5
16.0
6.5
Output buffer enable/disable delay
0.0
0.0
Product Term Control Delays
t
t
t
Product term clock delay
Product term set/reset delay
Product term 3-state delay
3.0
2.0
4.5
3.0
2.5
3.5
2.5
3.0
5.0
2.5
3.0
5.0
ns
ns
ns
PTCK
PTSR
PTTS
Internal Register and Combinatorial delays
t
t
t
t
t
t
t
Combinatorial logic propagation delay
Register setup time
0.5
1.0
3.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
PDI
SUI
HI
1.5
3.0
2.5
3.5
3.5
4.5
3.5
6.5
Register hold time
Register clock to output valid time
Register async. S/R to output delay
0.5
6.5
0.5
7.0
0.5
8.0
0.5
8.0
COI
AOI
RAI
LOGI
Register async. S/R recovery before clock 7.5
Internal logic delay
10.0
10.0
10.0
2.0
2.5
3.0
3.0
tLOGILP
Internal low power logic delay
10.0
11.0
11.5
11.5
Feedback Delays
t
t
FastCONNECT matrix feedback delay
Function Block local feeback delay
8.0
4.0
9.5
3.5
11.0
3.5
13.0
5.0
ns
ns
F
LF
Time Adders
3
t
t
Incremental Product Term Allocator delay
Slew-rate limited delay
1.0
4.0
1.0
4.5
1.0
5.0
1.5
5.5
ns
ns
PTA
SLEW
Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet.
December 4, 1998 (Version 3.0)
5
XILINX [ XILINX, INC ]
