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Virtex-5 Family Overview
Virtex-5 FPGA Logic
550 MHz Integrated Block Memory
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On average, one to two speed grade improvement over
Virtex-4 devices
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Up to 16.4 Mbits of integrated block memory
36-Kbit blocks with optional dual 18-Kbit mode
True dual-port RAM cells
Independent port width selection (x1 to x72)
Cascadable 32-bit variable shift registers or 64-bit
distributed memory capability
Superior routing architecture with enhanced diagonal
routing supports block-to-block connectivity with
minimal hops
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Up to x36 total per port for true dual port operation
Up to x72 total per port for simple dual port operation
(one Read port and one Write port)
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Memory bits plus parity/sideband memory support for
x9, x18, x36, and x72 widths
Configurations from 32K x 1 to 512 x 72
(8K x 4 to 512 x 72 for FIFO operation)
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Up to 330,000 logic cells including:
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Up to 207,360 internal fabric flip-flops with clock enable
(XC5VLX330)
Up to 207,360 real 6-input look-up tables (LUTs) with
greater than 13 million total LUT bits
Two outputs for dual 5-LUT mode gives enhanced
utilization
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Multirate FIFO support logic
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Full and Empty flag with fully programmable Almost Full
and Almost Empty flags
Logic expanding multiplexers and I/O registers
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Synchronous FIFO support without Flag uncertainty
Optional pipeline stages for higher performance
Byte-write capability
550 MHz Clock Technology
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Up to six Clock Management Tiles (CMTs)
Dedicated cascade routing to form 64K x 1 memory
without using FPGA routing
Integrated optional ECC for high-reliability memory
requirements
Special reduced-power design for 18 Kbit (and below)
operation
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Each CMT contains two DCMs and one PLL—up to
eighteen total clock generators
Flexible DCM-to-PLL or PLL-to-DCM cascade
Precision clock deskew and phase shift
Flexible frequency synthesis
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Multiple operating modes to ease performance trade-off
decisions
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Improved maximum input/output frequency
Fine-grained phase shifting resolution
Input jitter filtering
Low-power operation
Wide phase shift range
550 MHz DSP48E Slices
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25 x 18 two’s complement multiplication
Optional pipeline stages for enhanced performance
Optional 48-bit accumulator for multiply accumulate
(MACC) operation with optional accumulator cascade
to 96-bits
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Differential clock tree structure for optimized low-jitter
clocking and precise duty cycle
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32 global clock networks
Regional, I/O, and local clocks in addition to global
clocks
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Integrated adder for complex-multiply or multiply-add
operation
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Optional bitwise logical operation modes
Independent C registers per slice
SelectIO Technology
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Up to 1,200 user I/Os
Fully cascadable in a DSP column without external
routing resources
Wide selection of I/O standards from 1.2V to 3.3V
Extremely high-performance
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ChipSync Source-Synchronous
Interfacing Logic
Up to 800 Mb/s HSTL and SSTL
(on all single-ended I/Os)
Up to 1.25 Gb/s LVDS (on all differential I/O pairs)
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Works in conjunction with SelectIO technology to
simplify source-synchronous interfaces
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True differential termination on-chip
Same edge capture at input and output I/Os
Extensive memory interface support
Per-bit deskew capability built into all I/O blocks
(variable delay line on all inputs and outputs)
Dedicated I/O and regional clocking resources (pins
and trees)
Built-in data serializer/deserializer logic with
corresponding clock divider support in all I/O
Networking/telecommunication interfaces up to
1.25 Gb/s per I/O
DS100 (v5.1) August 21, 2015
www.xilinx.com
Product Specification
3
XILINX [ XILINX, INC ]
