0
R
XC4000XLA/XV Field Programmable
Gate Arrays
0
0*
DS015 (v1.3) October 18, 1999
Product Specification
XC4000XLA/XV Family Features
Note:
XC4000XLA devices are improved versions of
XC4000XL devices. The XC4000XV devices have the
same features as XLA devices, incorporate additional inter-
connect resources and extend gate capacity to 500,000
system gates. The XC4000XV devices require a separate
2.5V power supply for internal logic but maintain 5V I/O
compatibility via a separate 3.3V I/O power supply. For
additional information about the XC4000XLA/XV device
architecture, refer to the XC4000E/X FPGA Series general
and functional descriptions.
• System-featured Field-Programmable Gate Arrays
- Select-RAM
TM
memory: on-chip ultra-fast RAM with
- Synchronous write option
- Dual-port RAM option
- Flexible function generators and abundant flip-flops
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• Flexible Array Architecture
• Low-power Segmented Routing Architecture
• Systems-oriented Features
- IEEE 1149.1-compatible boundary scan
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- Unlimited reprogrammability
• Read Back Capability
- Program verification and internal node observability
Table 1: XC4000XLA Series Field Programmable Gate Arrays
*
Electrical Features
• XLA Devices Require 3.0 - 3.6 V (VCC)
• XV Devices Require 2.3- 2.7 V (VCCINT)
and 3.0 - 3.6 V (VCCIO)
• 5.0 V TTL compatible I/O
• 3.3 V LVTTL, LVCMOS compliant I/O
• 5.0 V and 3.0 V PCI Compliant I/O
• 12 mA or 24 mA Current Sink Capability
• Safe under All Power-up Sequences
• XLA Consumes 40% Less Power than XL
• XV Consumes 65% Less Power than XL
• Optional Input Clamping to VCC (XLA) or VCCIO (XV)
Additional Features
• Footprint Compatible with XC4000XL FPGAs - Lower
cost with improved performance and lower power
• Advanced Technology — 5 layer metal, 0.25
µm
CMOS
process (XV) or 0.35
µm
CMOS process (XLA)
• Highest Performance — System erformance beyond
100 MHz
• High Capacity — Up to 500,000 system gates and
270,000 synchronous SRAM bits
• Low Power — 3.3 V/2.5 V technology plus segmented
routing architecture
• Safe and Easy to Use — Interfaces to any combination
of 3.3 V and 5.0 V TTL compatible devices
6
Device
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC40110XV
XC40150XV
XC40200XV
XC40250XV
Logic
Cells
1,368
1,862
2,432
3,078
3,800
4,598
5,472
7,448
9,728
12,312
16,758
20,102
Max Logic Max. RAM
Typical
Gates
Bits
Gate Range
(No RAM) (No Logic) (Logic and RAM)*
13,000
18,432
10,000 - 30,000
20,000
28,000
36,000
44,000
52,000
62,000
85,000
110,000
150,000
200,000
250,000
25,088
32,768
41,472
51,200
61,952
73,728
100,352
131,072
165,888
225,792
270,848
13,000 - 40,000
18,000 - 50,000
22,000 - 65,000
27,000 - 80,000
33,000 - 100,000
40,000 - 130,000
55,000 - 180,000
75,000 - 235,000
100,000 - 300,000
130,000 - 400,000
180,000 - 500,000
CLB
Matrix
24 x 24
28 x 28
32 x 32
36 x 36
40 x 40
44 x 44
48 x 48
56 x 56
64 x 64
72 x 72
84 x 84
92 x 92
Total
CLBs
576
784
1,024
1,296
1,600
1,936
2,304
3,136
4,096
5,184
7,056
8,464
Number
of
Flip-Flops
1,536
2,016
2,560
3,168
3,840
4,576
5,376
7,168
9,216
11,520
15,456
18,400
Required
Max.
Configur-
User I/O ation Bits
192
393,632
224
256
288
320
352
384
448
448
448
448
448
521,880
668,184
832,528
1,014,928
1,215,368
1,433,864
1,924,992
2,686,136
3,373,448
4,551,056
5,433,888
*
Maximum values of gate range assume 20-30% of CLBs used as RAM
DS015 (v1.3) October 18, 1999 - Product Specification
6-157
XILINX [ XILINX, INC ]
