XC4000, XC4000A, XC4000H Logic Cell Array Families
C1
C2
C3
C4
H1
DIN
S/R
EC
G4
DIN
F'
G'
H'
S/R
CONTROL
LOGIC
FUNCTION
G'
OF
G1-G4
SD
BYPASS
YQ
Q
G3
D
G2
G1
LOGIC
FUNCTION
OF
H'
F', G',
AND
H1
F4
DIN
F'
G'
H'
EC
G'
H'
1
Y
RD
S/R
CONTROL
LOGIC
FUNCTION
F'
OF
F1-F4
D
SD
Q
BYPASS
XQ
F3
F2
F1
EC
RD
K
(CLOCK)
H'
F'
MULTIPLEXER CONTROLLED
BY CONFIGURATUON PROGRAM
X6099
1
X
Figure 1. Simplified Block Diagram of XC4000-Families Configurable Logic Block
independently for each of the two registers; this input also
can be disabled for either flip-flop. A separate global Set/
Reset line (not shown in Figure 1) sets or clears each
register during power-up, reconfiguration, or when a dedi-
cated Reset net is driven active. This Reset net does not
compete with other routing resources; it can be connected
to any package pin as a global reset input.
Each flip-flop can be triggered on either the rising or falling
clock edge. The source of a flip-flop data input is program-
mable: it is driven either by the functions F', G', and H', or
the Direct In (DIN) block input . The flip-flops drive the XQ
and YQ CLB outputs.
In addition, each CLB F' and G' function generator con-
tains dedicated arithmetic logic for the fast generation of
carry and borrow signals, greatly increasing the efficiency
and performance of adders, subtracters, accumulators,
comparators and even counters.
Multiplexers in the CLB map the four control inputs, la-
beled C1 through C4 in Figure 1, into the four internal
control signals (H1, DIN, S/R, and EC) in any arbitrary
manner.
The flexibility and symmetry of the CLB architecture facili-
tates the placement and routing of a given application.
Since the function generators and flip-flops have inde-
pendent inputs and outputs, each can be treated as a
separate entity during placement to achieve high packing
density. Inputs, outputs, and the functions themselves can
freely swap positions within a CLB to avoid routing conges-
tion during the placement and routing operation.
2-10
XILINX [ XILINX, INC ]
