Detailed Functional Description
XC4000 and XC4000A Input/Output Blocks
(For XC4000H family, see page 2-82)
The IOB forms the interface between the internal logic and
the I/O pads of the LCA device. Under configuration con-
trol, the output buffer receives either the logic signal (.out)
routed from the internal logic to the IOB, or the complement
of this signal, or this same data after it has been clocked
into the output flip-flop.
As a configuration option, each flip-flop (CLB or IOB) is
initialized as either set or reset, and is also forced into this
programmable initialization state whenever the global Set/
Reset net is activated after configuration has been com-
pleted. The clock polarity of each IOB flip-flop can be
configured individually, as can the polarity of the 3-state
control for the output buffer.
Each output buffer can be configured to be either fast or
slew-rate limited, which reduces noise generation and
ground bounce. Each I/O pin can be configured with either
an internal pull-up or pull down resistor, or with no internal
resistor. Independent of this choice, each IOB has a pull-
up resistor during the configuration process.
The 3-state output driver uses a totem pole n-channel
output structure. V
OH
is one n-channel threshold lower
than V
CC
, which makes rise and fall delays more
symmetrical.
Family
XC4000
XC4000A
XC4000H
Per IOB
Source
4
4
4
Per IOB
Sink
12
24
24*
Per IOB
Pair Sink
24
48
48
# Slew
Modes
2
4
2
*XC4000H devices can sink only 4 mA configured for SoftEdge mode
EXTEST
TS INV
TS/OE
Boundary
Scan
OUTPUT
INVERT
OUTPUT
M
sd
Ouput Data O
M
Ouput Clock OK
rd
M
S/R
INVERT
M
OUT
SEL
D
Q
TS - capture
TS - update
M
SLEW
RATE
PULL
DOWN
PULL
UP
3-State TS
V
CC
PAD
Boundary
Scan
O - capture
Q - capture
O - update
I - capture
Boundary
Scan
I - update
sd
D
DELAY
M
FLIP-FLOP/LATCH
Input Clock IK
M
INPUT
S/R
rd
M
INVERT
Q
Q
L
M M
M M
Input Data 2 I2
Input Data 1 I1
GLOBAL
S/R
X3025
Figure 11. XC4000 and XC4000A I/O Block
2-19
XILINX [ XILINX, INC ]
