®
XC4000, XC4000A, XC4000H
Logic Cell Array Families
Product Description
Features
Description
The XC4000 families of Field-Programmable Gate Arrays
(FPGAs) provide the benefits of custom CMOS VLSI, while
avoiding the initial cost, time delay, and inherent risk of a
conventional masked gate array.
The XC4000 families provide a regular, flexible, program-
mable architecture of Configurable Logic Blocks (CLBs),
interconnected by a powerful hierarchy of versatile routing
resources, and surrounded by a perimeter of program-
mable Input/Output Blocks (IOBs).
XC4000-family devices have generous routing resources to
accommodate the most complex interconnect patterns.
XC4000A devices have reduced sets of routing resources,
sufficient for their smaller size. XC4000H high I/O devices
maintain the same routing resources and CLB structure as
the XC4000 family, while nearly doubling the available I/O.
The devices are customized by loading configuration data
into the internal memory cells. The FPGA can either actively
read its configuration data out of external serial or byte-
parallel PROM (master modes), or the configuration data
can be written into the FPGA (slave and peripheral modes).
The XC4000 families are supported by powerful and so-
phisticated software, covering every aspect of design: from
schematic entry, to simulation, to automatic block place-
ment and routing of interconnects, and finally the creation
of the configuration bit stream.
Since Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications. FPGAs
are ideal for shortening the design and development cycle,
but they also offer a cost-effective solution for production
rates well beyond 1000 systems per month.
•
Third Generation Field-Programmable Gate Arrays
–
–
–
–
–
–
–
–
Abundant flip-flops
Flexible function generators
On-chip ultra-fast RAM
Dedicated high-speed carry-propagation circuit
Wide edge decoders
Hierarchy of interconnect lines
Internal 3-state bus capability
Eight global low-skew clock or signal distribution
network
•
Flexible Array Architecture
– Programmable logic blocks and I/O blocks
– Programmable interconnects and wide decoders
•
Sub-micron CMOS Process
– High-speed logic and Interconnect
– Low power consumption
•
Systems-Oriented Features
– IEEE 1149.1-compatible boundary-scan logic support
– Programmable output slew rate
– Programmable input pull-up or pull-down resistors
– 12-mA sink current per output (XC4000 family)
– 24-mA sink current per output (XC4000A and
XC4000H families)
•
Configured by Loading Binary File
– Unlimited reprogrammability
– Six programming modes
•
XACT Development System runs on ’386/’486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700
series
– Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
– Fully automatic partitioning, placement and routing
– Interactive design editor for design optimization
– 288 macros, 34 hard macros, RAM/ROM compiler
Table 1. The XC4000 Families of Field-Programmable Gate Arrays
Device
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs
(per side)
Max RAM Bits
Number of IOBs
XC4002A 4003/3A 4003H
2,000
8x8
64
256
24
2,048
64
4004A 4005/5A 4005H
4006
4008
4010/10D 4013/13D 4020
10,000
20 x 20
400
1,120
60
12,800*
160
4025
3,000
3,000
4,000
5,000
5,000 6,000
8,000
10 x 10 10 x 10 12 x 12 14 x 14 14 x 14 16 x 16 18 x 18
100
100
144
196
196
256
324
360
200
480
616
392
768
936
30
30
36
42
42
48
54
3,200
80
3,200
160
4,608
96
6,272
112
6,272
192
8,192
128
10,368
144
13,000 20,000 25,000
24 x 24 28 x 28 32 x 32
576
784
1,024
1,536
2,016
2,560
72
84
96
18,432*
192
25,088
224
32,768
256
*XC4010D and XC4013D have no RAM
2-7