Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, there derived from benchmark timing patterns. The following
guidelines relflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Full length, both pull-ups,
inputs from IOB I-pins
Symbol
T
WAF
Device
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
-6
Max
8.5
9.0
9.5
10.0
11.5
12.0
12.5
13.0
8.5
9.0
9.5
10.0
11.5
12.0
12.5
13.0
-5
Max
7.5
8.0
8.5
9.0
10.5
11.0
11.5
12.0
7.5
8.0
8.5
9.0
10.5
11.0
11.5
12.0
PRELIMINARY
-4
Max
5.0
6.0
7.0
8.0
6.0
7.0
8.0
9.0
Max
5.7
5.8
5.9
6.0
6.7
6.8
6.9
7.0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Full length, both pull-ups
inputs from internal logic
T
WAFL
Half length, one pull-up
inputs from IOB I-pins
T
WAO
Half length, one pull-up
inputs from internal logic
T
WAOL
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (T
PID
)
and output delay (one of 4 modes), as listed on page 2-70.
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Global Signal Distribution
From pad through
primary
buffer, to any clock k
Symbol
T
PG
Device
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
Max
7.7
7.8
7.9
8.0
8.7
8.8
8.9
9.0
PRELIMINARY
5.1
5.5
6.3
6.7
Speed Grade
-6
-5
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
From pad through
secondary
buffer, to any clock k
T
SG
2-73
XILINX [ XILINX, INC ]
