Pinout Descriptions
User I/Os by Bank
Table 78 and Table 79 indicate how the available user-I/O
pins are distributed between the four I/O banks on the
FG320 package. The AWAKE pin is counted as a
dual-purpose I/O.
Table 78: User I/Os Per Bank for XC3S200A in the FG320 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
I/O
35
9
INPUT
DUAL
1
VREF
CLK
8
Top
0
1
2
3
60
64
11
10
6
5
7
Right
Bottom
Left
30
21
0
8
60
19
38
101
6
8
64
13
40
5
8
TOTAL
248
52
23
32
Table 79: User I/Os Per Bank for XC3S400A in the FG320 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
I/O
35
9
INPUT
DUAL
1
VREF
CLK
8
Top
0
1
2
3
61
64
12
10
7
5
7
Right
Bottom
Left
30
21
0
8
62
19
38
101
7
8
64
13
42
5
8
TOTAL
251
52
24
32
Footprint Migration Differences
Table 80 summarizes any footprint and functionality
differences between the XC3S200A and the XC3S400A
FPGAs that might affect easy migration between devices
available in the FG320 package. There are three such balls.
All other pins not listed in Table 80 unconditionally migrate
between Spartan-3A devices available in the FG320
package.
The arrows indicate the direction for easy migration.
Table 80: FG320 Footprint Migration Differences
Pin
E13
N7
Bank
XC3S200A
N.C.
Migration
XC3S400A
INPUT
0
2
2
Æ
Æ
Æ
3
N.C.
N.C.
INPUT
P14
INPUT/VREF
DIFFERENCES
Legend:
This pin can unconditionally migrate from the device
on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
configured for the device on the right.
Æ
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
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XILINX [ XILINX, INC ]
