Pinout Descriptions
User I/Os by Bank
Table 84 and Table 85 indicate how the user-I/O pins are
distributed between the four I/O banks on the FG484
package. The AWAKE pin is counted as a dual-purpose I/O.
Table 84: User I/Os Per Bank for the XC3S700A in the FG484 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
58
INPUT
17
DUAL
1
VREF
CLK
8
Top
0
1
2
3
92
94
8
8
Right
Bottom
Left
33
15
30
21
0
8
92
43
11
9
8
94
61
17
8
8
TOTAL
372
195
60
52
33
32
Table 85: User I/Os Per Bank for the XC3S1400A in the FG484 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
58
INPUT
DUAL
1
VREF
CLK
8
Top
0
1
2
3
92
94
17
15
13
17
62
8
8
Right
Bottom
Left
33
30
21
0
8
95
43
10
8
8
94
61
8
TOTAL
375
195
52
34
32
Footprint Migration Differences
Table 86 summarizes any footprint and functionality
differences between the XC3S700A and the XC3S1400A
FPGAs that might affect easy migration between devices
available in the FG484 package. There are three such balls.
All other pins not listed in Table 86 unconditionally migrate
between Spartan-3A devices available in the FG484
package.
The arrows indicate the direction for easy migration.
Table 86: FG484 Footprint Migration Differences
Pin
T8
Bank
XC3S700A
N.C.
Migration
XC3S1400A
INPUT/VREF
INPUT
2
2
2
Æ
Æ
Æ
3
U7
N.C.
N.C.
U16
INPUT
DIFFERENCES
Legend:
This pin can unconditionally migrate from the device
on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
configured for the device on the right.
Æ
116
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DS529-4 (v2.0) August 19, 2010
XILINX [ XILINX, INC ]
