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XC3S500E-4FTG256CS1 参数 Datasheet PDF下载

XC3S500E-4FTG256CS1图片预览
型号: XC3S500E-4FTG256CS1
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 572MHz, 10476-Cell, CMOS, PBGA256,]
分类和应用: 时钟可编程逻辑
文件页数/大小: 227 页 / 6528 K
品牌: XILINX [ XILINX, INC ]
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Spartan-3E FPGA Family: Pinout Descriptions  
User I/Os by Bank  
Table 137 and Table 138 indicate how the 108 available  
user-I/O pins are distributed between the four I/O banks on  
the TQ144 package.  
Table 137: User I/Os Per Bank for the XC3S100E in the TQ144 Package  
All Possible I/O Pins by Type  
Package  
Edge  
I/O Bank  
Maximum I/O  
(2)  
I/O  
9
INPUT  
DUAL  
1
VREF(1)  
CLK  
Top  
0
1
2
3
26  
28  
6
5
2
2
2
3
9
8
Right  
0
21  
20  
0
0(2)  
0(2)  
8
Bottom  
Left  
26  
0
4
28  
13  
22  
4
TOTAL  
108  
19  
42  
16  
Notes:  
1. Some VREF and CLK pins are on INPUT pins.  
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.  
Table 138: User I/Os Per Bank for the XC3S250E in TQ144 Package  
All Possible I/O Pins by Type  
Package  
Edge  
I/O Bank  
Maximum I/O  
(2)  
I/O  
9
INPUT  
DUAL  
1
VREF(1)  
CLK  
Top  
0
1
2
3
26  
28  
6
5
2
2
2
3
9
8
Right  
0
21  
20  
0
0(2)  
0(2)  
8
Bottom  
Left  
26  
0
4
28  
11  
20  
6
TOTAL  
108  
21  
42  
16  
Notes:  
1. Some VREF and CLK pins are on INPUT pins.  
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.  
The arrows indicate the direction for easy migration. For  
example, a left-facing arrow indicates that the pin on the  
XC3S250E unconditionally migrates to the pin on the  
XC3S100E. It may be possible to migrate the opposite  
direction depending on the I/O configuration. For example,  
an I/O pin (Type = I/O) can migrate to an input-only pin  
(Type = INPUT) if the I/O pin is configured as an input.  
Footprint Migration Differences  
Table 139 summarizes any footprint and functionality  
differences between the XC3S100E and the XC3S250E  
FPGAs that may affect easy migration between devices.  
There are four such pins. All other pins not listed in  
Table 139 unconditionally migrate between Spartan-3E  
devices available in the TQ144 package.  
Table 139: TQ144 Footprint Migration Differences  
TQ144 Pin  
P10  
Bank  
XC3S100E Type  
Migration  
XC3S250E Type  
INPUT  
3
3
3
2
I/O  
I/O  
4
P29  
INPUT  
P31  
VREF(INPUT)  
VREF(INPUT)  
VREF(I/O)  
VREF(I/O)  
P66  
DIFFERENCES  
Legend:  
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may  
be possible depending on how the pin is configured for the device on the right.  
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may  
be possible depending on how the pin is configured for the device on the left.  
DS312 (v4.2) December 14, 2018  
www.xilinx.com  
Product Specification  
178  
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