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Spartan-3E FPGA Family:
Functional Description
DS312 (v4.2) December 14, 2018
Product Specification
Design Documentation Available
Xilinx Alerts
The functionality of the Spartan®-3E FPGA family is now
described and updated in the following documents. The
topics covered in each guide are listed below.
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automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
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UG331: Spartan-3 Generation FPGA User Guide
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Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Spartan-3E FPGA Starter Kit
Configurable Logic Blocks (CLBs)
For specific hardware examples, please see the Spartan-3E
FPGA Starter Kit board web page, which has links to
various design examples and the user guide.
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Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
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Spartan-3E FPGA Starter Kit Board page
http://www.xilinx.com/s3estarter
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I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Design Tools
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UG230: Spartan-3E FPGA Starter Kit User Guide
IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
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UG332: Spartan-3 Generation Configuration User
Guide
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Configuration Overview
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Configuration Pins and Behavior
Bitstream Sizes
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Detailed Descriptions by Mode
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Master Serial Mode using Xilinx® Platform
Flash PROM
Master SPI Mode using Commodity SPI Serial
Flash PROM
Master BPI Mode using Commodity Parallel
NOR Flash PROM
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Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
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ISE iMPACT Programming Examples
MultiBoot Reconfiguration
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DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
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