Spartan-3E FPGA Family: Functional Description
In SPI Serial Flash mode (M[2:0] = <0:0:1>), the Spartan-3E
FPGA configures itself from an attached industry-standard
SPI serial Flash PROM, as illustrated in Figure 53 and
Figure 54. The FPGA supplies the CCLK output clock from
its internal oscillator to the clock input of the attached SPI
Flash PROM.
SPI Serial Flash Mode
For additional information, refer to the “Master SPI Mode”
chapter in UG332.
X-Ref Target - Figure 53
+1.2V
+3.3V
SPI
Serial
Flash
VCCINT
P
P
HSWAP
VCCO_0
VCCO_0
I
VCC
DATA_IN
VCCO_2
MOSI
+3.3V
SPI Mode
DIN
DATA_OUT
SELECT
‘0’
‘0’
‘1’
M2
M1
M0
CSO_B
WR_PROTECT
HOLD
W
‘1’
Spartan-3E
CLOCK
Variant Select
FPGA
GND
‘1’
S
VS2
VS1
VS0
+3.3V
‘1’
CCLK
DOUT
INIT_B
+2.5V
JTAG
TDI
+2.5V
VCCAUX
TDO
+2.5V
TDI
TMS
TCK
TDO
TMS
TCK
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_46_082009
Figure 53: SPI Flash PROM Interface for PROMs Supporting READ (0x03) and FAST_READ (0x0B) Commands
S
Although SPI is a standard four-wire interface, various
Serial Peripheral Interface (SPI) Configuration Timing in
Module 3.
available SPI Flash PROMs use different command
protocols. The FPGA’s variant select pins, VS[2:0], define
how the FPGA communicates with the SPI Flash, including
which SPI Flash command the FPGA issues to start the
read operation and the number of dummy bytes inserted
before the FPGA expects to receive valid data from the SPI
Flash. Table 53 shows the available SPI Flash PROMs
expected to operate with Spartan-3E FPGAs. Other
compatible devices might work but have not been tested for
suitability with Spartan-3E FPGAs. All other VS[2:0] values
are reserved for future use. Consult the data sheet for the
desired SPI Flash device to determine its suitability. The
basic timing requirements and waveforms are provided in
Figure 53 shows the general connection diagram for those
SPI Flash PROMs that support the 0x03 READ command
or the 0x0B FAST READ commands.
Figure 54 shows the connection diagram for Atmel
DataFlash serial PROMs, which also use an SPI-based
protocol. ‘B’-series DataFlash devices are limited to FPGA
applications operating over the commercial temperature
range. Industrial temperature range applications must use
‘C’- or ‘D’-series DataFlash devices, which have a shorter
DataFlash select setup time, because of the faster FPGA
CCLK frequency at cold temperatures.
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
75
XILINX [ XILINX, INC ]
