Spartan-3E FPGA Family: Functional Description
The SLICEM pair supports two additional functions:
Enable (CE), Slice Write Enable (SLICEWE1), and
Reset/Set (RS) are shared in common between the two
halves.
•
•
Two 16x1 distributed RAM blocks, RAM16
Two 16-bit shift registers, SRL16
The LUTs located in the top and bottom portions of the slice
are referred to as “G” and “F”, respectively, or the “G-LUT”
and the “F-LUT”. The storage elements in the top and
bottom portions of the slice are called FFY and FFX,
respectively.
Each of these elements is described in more detail in the
following sections.
Logic Cells
Each slice has two multiplexers with F5MUX in the bottom
portion of the slice and FiMUX in the top portion. Depending
on the slice, the FiMUX takes on the name F6MUX,
F7MUX, or F8MUX, according to its position in the
multiplexer chain. The lower SLICEL and SLICEM both
have an F6MUX. The upper SLICEM has an F7MUX, and
the upper SLICEL has an F8MUX.
The combination of a LUT and a storage element is known
as a “Logic Cell”. The additional features in a slice, such as
the wide multiplexers, carry logic, and arithmetic gates, add
to the capacity of a slice, implementing logic that would
otherwise require additional LUTs. Benchmarks have
shown that the overall slice is equivalent to 2.25 simple logic
cells. This calculation provides the equivalent logic cell
count shown in Table 9.
The carry chain enters the bottom of the slice as CIN and
exits at the top as COUT. Five multiplexers control the chain:
CYINIT, CY0F, and CYMUXF in the bottom portion and
CY0G and CYMUXG in the top portion. The dedicated
arithmetic logic includes the exclusive-OR gates XORF and
XORG (bottom and top portions of the slice, respectively)
as well as the AND gates FAND and GAND (bottom and top
portions, respectively).
Slice Details
Figure 15 is a detailed diagram of the SLICEM. It represents
a superset of the elements and connections to be found in
all slices. The dashed and gray lines (blue when viewed in
color) indicate the resources found only in the SLICEM and
not in the SLICEL.
See Table 10 for a description of all the slice input and
output signals.
Each slice has two halves, which are differentiated as top
and bottom to keep them distinct from the upper and lower
slices in a CLB. The control inputs for the clock (CLK), Clock
Table 10: Slice Inputs and Outputs
Name
F[4:1]
Location
SLICEL/M Bottom
SLICEL/M Top
Direction
Input
Description
F-LUT and FAND inputs
G[4:1]
BX
Input
G-LUT and GAND inputs or Write Address (SLICEM)
SLICEL/M Bottom
Input
Bypass to or output (SLICEM) or storage element, or control input to F5MUX,
input to carry logic, or data input to RAM (SLICEM)
BY
SLICEL/M Top
Input
Bypass to or output (SLICEM) or storage element, or control input to FiMUX,
input to carry logic, or data input to RAM (SLICEM)
BXOUT
BYOUT
ALTDIG
DIG
SLICEM Bottom
SLICEM Top
Output
Output
Input
BX bypass output
BY bypass output
SLICEM Top
Alternate data input to RAM
SLICEM Top
Output
Input
ALTDIG or SHIFTIN bypass output
RAM Write Enable
SLICEWE1
F5
SLICEM Common
SLICEL/M Bottom
SLICEL/M Top
SLICEL/M Top
SLICEL/M Top
SLICEL/M Common
SLICEL/M Common
SLICEL/M Common
SLICEM Top
Output
Input
Output from F5MUX; direct feedback to FiMUX
Input to FiMUX; direct feedback from F5MUX or another FiMUX
Input to FiMUX; direct feedback from F5MUX or another FiMUX
Output from FiMUX; direct feedback to another FiMUX
FFX/Y Clock Enable
FXINA
FXINB
Fi
Input
Output
Input
CE
SR
Input
FFX/Y Set or Reset or RAM Write Enable (SLICEM)
FFX/Y Clock or RAM Clock (SLICEM)
Data input to G-LUT RAM
CLK
Input
SHIFTIN
Input
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
24
XILINX [ XILINX, INC ]
