Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 8
and the rising edge of OCLK2 (= D2), which is typically the
same as the falling edge of OCLK1. These two bits of data
are multiplexed by the DDR mux and forwarded to the
output pin. The D2 data signal must be re-synchronized
from the OCLK1 clock domain to the OCLK2 domain using
FPGA slice flip-flops. Placement is critical at high
frequencies, because the time available is only one half a
clock cycle. See Figure 10 for a graphical illustration of this
function.
Q
Q
D
D
D1
PAD
To Fabric
D2
ICLK2
ICLK1
The C0 or C1 alignment feature of the ODDR2 flip-flop,
originally introduced in the Spartan-3E FPGA family, is not
recommended or supported in the ISE development
software. The ODDR2 flip-flop without the alignment feature
remains fully supported. Without the alignment feature, the
ODDR2 feature behaves equivalent to the ODDR flip-flop
on previous Xilinx FPGA families.
ICLK1
ICLK2
PAD
D1
d
d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8
d+2 d+4 d+6
d
d+8
d+7
X-Ref Target - Figure 10
D2 d-1
d+1
d+3
d+5
Q
D
D1
PAD
DS312-2_21_021105
From
Fabric
Figure 8: Input DDR (without Cascade Feature)
In the Spartan-3E device, the signal D2 can be cascaded
into the storage element of the adjacent slave IOB. There it
is re-registered to ICLK1, and only then fed to the FPGA
fabric where it is now already in the same time domain as
D1. Here, the FPGA fabric uses only the clock ICLK1 to
process the received data. See Figure 9 for a graphical
illustration of this function.
D2
Q
D
OCLK1
OCLK2
X-Ref Target - Figure 9
OCLK1
Q
D
D1
OCLK2
D1
PAD
d
d+2
d+4
d+6
d+8
d+10
d+9
To Fabric
D2
D2
d+1
d+3
d+5
d+7
d+5 d+6
IDDRIN2
IQ2
Q
D
Q
D
d+8
PAD
d+7
d
d+1 d+2 d+3 d+4
DS312-2_23_030105
Figure 10: Output DDR
ICLK1
ICLK2
SelectIO Signal Standards
The Spartan-3E I/Os feature inputs and outputs that
support a wide range of I/O signaling standards (Table 6
and Table 7). The majority of the I/Os also can be used to
form differential pairs to support any of the differential
signaling standards (Table 7).
ICLK1
ICLK2
d
d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8
PAD
D1
d
d+2
d+1
d+4
d+3
d+6
d+5
d+8
d+7
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to the Xilinx Software Manuals and
Help.
D2
d-1
DS312-2_22_030105
Figure 9: Input DDR Using Spartan-3E Cascade Feature
ODDR2
As a DDR output pair, the master IOB registers data coming
from the FPGA fabric on the rising edge of OCLK1 (= D1)
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
15
XILINX [ XILINX, INC ]
