R
Functional Description
This is accomplished by taking data synchronized to the
clock signal’s rising edge and converting it to bits syn-
chronized on both the rising and the falling edge. The com-
bination of two registers and a multiplexer is referred to as a
Double-Data-Rate D-type flip-flop (ODDR2).
Storage Element Functions
There are three pairs of storage elements in each IOB, one
pair for each of the three paths. It is possible to configure
each of these storage elements as an edge-triggered
D-type flip-flop (FD) or a level-sensitive latch (LD).
Table 1 describes the signal paths associated with the stor-
age element.
The storage-element pair on either the Output path or the
Three-State path can be used together with a special multi-
plexer to produce Double-Data-Rate (DDR) transmission.
Table 1: Storage Element Signal Description
Storage
Element
Signal
Description
Data input
Function
D
Data at this input is stored on the active edge of CK and enabled by CE. For latch
operation when the input is enabled, data passes directly to the output Q.
Q
Data output
The data on this output reflects the state of the storage element. For operation as a latch
in transparent mode, Q mirrors the data at D.
CK
CE
Clock input
Data is loaded into the storage element on this input’s active edge with CE asserted.
Clock Enable input
When asserted, this input enables CK. If not connected, CE defaults to the asserted
state.
SR
Set/Reset input
Reverse input
This input forces the storage element into the state specified by the SRHIGH/SRLOW
attributes. The SYNC/ASYNC attribute setting determines if the SR input is
synchronized to the clock or not. If both SR and REV are active at the same time, the
storage element gets a value of 0.
REV
This input is used together with SR. It forces the storage element into the state opposite
from what SR does. The SYNC/ASYNC attribute setting determines whether the REV
input is synchronized to the clock or not. If both SR and REV are active at the same time,
the storage element gets a value of 0.
trols the CE inputs for the register pair on the three-state
path and ICE does the same for the register pair on the
input path.
As shown in Figure 1, the upper registers in both the output
and three-state paths share a common clock. The OTCLK1
clock signal drives the CK clock inputs of the upper registers
on the output and three-state paths. Similarly, OTCLK2
drives the CK inputs for the lower registers on the output
and three-state paths. The upper and lower registers on the
input path have independent clock lines: ICLK1 and ICLK2.
The Set/Reset (SR) line entering the IOB controls all six
registers, as is the Reverse (REV) line.
In addition to the signal polarity controls described in IOB
Overview, each storage element additionally supports the
controls described in Table 2.
The OCE enable line controls the CE inputs of the upper
and lower registers on the output path. Similarly, TCE con-
Table 2: Storage Element Options
Option Switch
Function
Specificity
FF/Latch
Chooses between an edge-triggered flip-flop
or a level-sensitive latch
Independent for each storage element
SYNC/ASYNC
Determines whether the SR set/reset control is Independent for each storage element
synchronous or asynchronous
4
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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