XC3S400-5PQ208I 参数 Datasheet PDF下载

Spartan-3 FPGA Family: Functional Description

R

T

T1

D

CE

CK

SR

Q

TFF1

REV

DDR

MUX

TCE

T2

D

CE

CK

SR

Q

TFF2

REV

Three-state Path

O1

D

CE

Q

OFF1

V

CCO

OTCLK1

CK

SR

Pull-Up

REV

DDR

MUX

ESD

I/O

Pin

OCE

O2

D

CE

OTCLK2

CK

SR

Q

OFF2

Program-

mable

Output

Driver

DCI

Pull-

Down

ESD

REV

Keeper

Latch

Output Path

IQ1

I

D

CE

ICLK1

ICE

CK

SR

Q

IFF1

Fixed

Delay

LVCMOS, LVTTL, PCI

Single-ended Standards

using VREF

V

REF

Pin

REV

Differential Standards

IQ2

D

CE

ICLK2

SR

REV

Input Path

Note: All IOB signals communicating with the FPGA's internal logic have the option of inverting polarity.

CK

SR

Q

IFF2

I/O Pin

from

Adjacent

IOB

REV

DS099-2_01_082104

Figure 1:

Simplified IOB Diagram

2

40

Preliminary Product Specification