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Spartan-3 FPGA Family:
Pinout Descriptions
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DS099-4 (v1.6) January 17, 2005
Product Specification
Introduction
This data sheet module describes the various pins on a
Spartan™-3 FPGA and how they connect to the supported
component packages.
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The Package Overview section describes the various
packaging options available for Spartan-3 FPGAs.
Detailed pin list tables and footprint diagrams are
provided for each package solution.
•
•
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The Pin Types section categorizes all of the FPGA
pins by their function type.
Pin Descriptions
The Pin Definitions section provides a top-level
description for each pin on the device.
The Detailed, Functional Pin Descriptions section
offers significantly more detail about each pin,
especially for the dual- or special-function pins used
during device configuration.
Pin Types
A majority of the pins on a Spartan-3 FPGA are gen-
eral-purpose, user-defined I/O pins. There are, however, up
to 12 different functional types of pins on Spartan-3 pack-
ages, as outlined in Table 1. In the package footprint draw-
ings that follow, the individual pins are color-coded
according to pin type as in the table.
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Some pins have associated 4 behavior, controlled by
settings in the configuration bitstream. These options
are described in the Bitstream Options section.
Table 1: Types of Pins on Spartan-3 FPGAs
Type/
Color
Code
Description
Unrestricted, general-purpose user-I/O pin. Most pins can be
paired together to form differential I/Os.
Pin Name(s) in Type
I/O
IO,
IO_Lxxy_#
DUAL
Dual-purpose pin used in some configuration modes during the IO_Lxxy_#/DIN/D0, IO_Lxxy_#/D1,
configuration process and then usually available as a user I/O IO_Lxxy_#/D2, IO_Lxxy_#/D3,
after configuration. If the pin is not used during configuration, this IO_Lxxy_#/D4, IO_Lxxy_#/D5,
pin behaves as an I/O-type pin. There are 12 dual-purpose
configuration pins on every package.
IO_Lxxy_#/D6, IO_Lxxy_#/D7,
IO_Lxxy_#/CS_B, IO_Lxxy_#/RDWR_B,
IO_Lxxy_#/BUSY/DOUT,
IO_Lxxy_#/INIT_B
CONFIG Dedicated configuration pin. Not available as a user-I/O pin.
Every package has seven dedicated configuration pins. These
pins are powered by VCCAUX.
CCLK, DONE, M2, M1, M0, PROG_B,
HSWAP_EN
JTAG
Dedicated JTAG pin. Not available as a user-I/O pin. Every
package has four dedicated JTAG pins. These pins are powered
by VCCAUX.
TDI, TMS, TCK, TDO
DCI
Dual-purpose pin that is either a user-I/O pin or used to calibrate IO/VRN_#
output buffer impedance for a specific bank using Digital
Controlled Impedance (DCI). There are two DCI pins per I/O
bank.
IO_Lxxy_#/VRN_#
IO/VRP_#
IO_Lxxy_#/VRP_#
VREF
Dual-purpose pin that is either a user-I/O pin or, along with all
IO/VREF_#
other VREF pins in the same bank, provides a reference voltage IO_Lxxy_#/VREF_#
input for certain I/O standards. If used for a reference voltage
within a bank, all VREF pins within the bank must be connected.
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099-4 (v1.6) January 17, 2005
Preliminary Product Specification
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